VLSI Job Seekers :: VLSI Training Institute in Bangalore

hiring Physical Design Trained Candidates at sivalleytech

Physical Design - Trained Candidates Eligibility :- B.Tech:- 2014, 2015, & 2016 Only (Above 65 %) M.Tech:- 2015 & 2016, 2017 & 2018 (Above 60 %) Physical Design Trained Candidates Only Intrested Candidates please drop your profile_ mpe@sivalleytech.com Immediate Joiners Preferable Any queries feel free to reach me...

Company : sivalleytech Location : bangalore Share Your Resume : mpe@sivalleytech.com

Entry Level VLSI fresher hire at cadence

cadence hire an Entry Level Candidate of IP DDR Core Team with an exp of 6 months to 2 yrs at Bangalore. Please send me your CV at rupa@cadence.com if interested

Company : cadence Location : bangalore Share Your Resume : rupa@cadence.com

hiring fresh Electronics Engineering Graduates at open silicon

looking for fresh Electronics Engineering Graduates to work as Technical Writer position for Bangalore location. Availability: immediate Interested candidates can share their CV at ridam.jaiswal@open-silicon.com

Company : opensilicon Location : bangalore Share Your Resume : ridam.jaiswal@open-silicon.com

VLSI Intern position open at Synopsys

FPGA Intern position open at Synopsys, Bangalore JD: New College graduates, B.E/B.Tech/M.E/M.Tech in Electronics or VLSI background. 1) Should have very good digital logic design knowledge. 2) Knowledge in Verilog/VHDL and FPGA design flow is required. 3) Good communication and inter-personal skills. 4) Exposure to Synplify or any FPGA synthesis software is a plus Interested candidates please mail your resume to akpv@synopsys.com

Company : synopsys Location : bangalore Share Your Resume : akpv@synopsys.com

hiring embedded freshers at prusys

IOT Engineers/Embedded System Engineers Job Requirements • Excellent grasp of data structures and embedded programming experience in using C++/Embedded C with any IOT communication protocol (Wifi, Modbus, Sensors etc) Python Scripting. • Excellent knowledge in using various types of Micro Controllers. • Knowledge in raspberry PI and Ardunio for prototyping. • Good understanding in Embedded/Cloud IoT application development using and developing REST APIs Knowledge of JSON Experience with developing drivers for communication standards. • Good interpersonal, communication, collaboration, and presentation skills. • Sincere, dedicated and responsible candidates Freshers/Interns with excellent knowledge and passion in IoT and embedded systems are welcome Please mail your cv at hr@prusys.com

Company : prusys Location : bangalore Share Your Resume : hr@prusys.com

hiring vlsi freshers blueberrysemiconductor

BLUEBERRYSEMI HIRING FRESHERS WITH 6 MONTHS OF TRAINING IN VLSI WHO ARE BASICALLY FROM AHMADABAD OR WILLING TO RELOCATE TO AHMEDABAD CAN SEND THEIR UPDATED RESUME TO: RESHMA@BLUEBERRYSEMI.COM LOCATION : AHMADABAD EXPERIENCE: 6 MONTHS OF TRAINING IMMEDIATE JOINERS ARE PREFERRED LOCATION FOR INTERVIEW : AHMEDABAD blueberry Semiconductors Pvt. Ltd.

Company : blueberrysemi Location : Ahemadabad Share Your Resume : reshma@blueberrysemi.com

Embedded fresher jobs Zilogic Systems

Zilogic Systems hiring for Candidates Completed Diploma Course in Embedded. Job Description: Designation: Embedded Developer - Strong in C Logical Programming - Knowledge in Embedded C tools and technologies. - Knowledge in ARMs and Protocols like I2C/SPI/UART/CAN - Good Communication Skills. Experience: 0 to 1.5 Year Qualifications: BE/B.Tech 2017/2018 Passed Outs Percentage: 70% + in all Academic Interview Location: Chennai Work Location: Chennai Interview Date: 5th January 2019 Notice Period: Immediate Joiners Walk-Ins Drive Venue: Zilogic Systems (Block-II), Plot No. 4, Judges Avenue, LB Road, Thiruvanmiyur, Chennai - 600 041. Interested Candidates can share your CV to hr@zilogic.com Contact Person: Gayathri Contact Details: 9962002103

Company : zilogic Location : chennai Share Your Resume : hr@zilogic.com

VLSI freshers walkins drive at graphsemi

VLSI freshers walkins drive .strong academic fundamental • Detailed understanding of project executed . • Strong in Vlsi fundamentals and digital electronics. • Strong problem solving and logical reasoning skills. • Good communication skills with lot of enthusiasm it? Qualification : M.tech , B.tech with 70 % 2018 passout interested can share cv @ talent@graphsemi.com

Company : graphsemi Location : bangalore Share Your Resume : talent@graphsemi.com

Zia Semiconductor Hiring VLSI freshers walk drive

Zia Semiconductor Hiring VLSI freshers e Zia Semiconductor would be conducting a walk-in drive for freshers on 10th Jan 2019. For the Domains of Design and Layout for ASIC IP design teams. The eligibility criteria would be 85% and above for 10th and 12th and 75% and above in Engineering. Interested candidates can attend the recruitment drive on the above mentioned date at Zia Semiconductor Pvt Ltd, #10, Hosur Road, Langford Town, Shanti Nagar, Near Confident Propus hotel, Bangalore 560025 The drive starts at 10:00am on 10th Jan 2019 Bangalore

Company : Zia Semiconductor Location : bangalore Share Your Resume : na

Skandysys hiring VLSI freshers

Skandysys is hiring freshers for the role of DFT Engineer. Interested candidates can apply to vaishnavi.m@skandysys.com. Following is the skillset required: 1.Digital Fundamentals and STA 2.Verilog 3.Python Scripting 4.Logical Skills.

Company : skandysys Location : bangalore Share Your Resume : vaishnavi.m@skandysys.com

hiring Embedded Software Professionals

Valeo India is hiring Embedded Software Professionals. Interviews @ Bangalore. Date : 19th & 20th of Jan 2019. Venue details shall be intimated shortly. Interested can send their resume to tacindia.in.mailbox@valeo.com

Company : valeo Location : bangalore Share Your Resume : tacindia.in.mailbox@valeo.com

hiring Verification Engineers

Openings Available for Verification Engineers Desired Exp : 2-10 years Job Location: Pune HDL/HVL: Conversant with VHDL, Verilog, System Verilog Methodologies: Exposure to standard methodologies viz. UVM, OVM Bus standards: AMBA, AHB, APB Processors: ARM architecture Standard peripherals such as I2C, SPI, UART, Timers, GPIO etc. Understanding of different coverage, Netlist simulations and debug. Opportunities are available in both IP level verification and SoC level Verification Please send your resume to vishal.patel@inedasystems.com

Company : inedasystems Location : bangalore Share Your Resume : vishal.patel@inedasystems.com

Graphene is hiring VLSI candidates

BTech / MTech only 2018 freshers with excellent academic records (70% & Above only) Very Strong in VLSI fundamentals Email to: swati.kaviraj@graphsemi.com

Company : graphsemi Location : bangalore Share Your Resume : swati.kaviraj@graphsemi.com

Hiring VLSI Freshers for Internship Open silicon

Hiring VLSI Freshers for Internship Open silicon ob Location: Bangalore Skills: C++, Python, Verilog Interested candidates can send their resume to careers.india@open-silicon.com

Company : Open Silicon Location : bangalore Share Your Resume : careers.india@open-silicon.com

hiring Fresh Embedded Engineers at faststreamtech

Faststream Technologies is hiring for the Embedded Trainee (Freshers) in Bangalore, Skills: Background in Systems Programming, Operating Systems, RTOS, FreeRTOS. Wi-Fi, Bluetooth development & BLE solutions. Experience in developing embedded devices, toys, robots, sensors, or control systems. Experience developing on ARM Cortex, MSP430, IMX6, AVR 8051, DSP, or other embedded platforms. Experience with codecs, ADCs & DACs. Communication protocols: I2C, SPI, USART, I2S, PCM.

Company : faststreamtech Location : bangalore Share Your Resume : ashish.rout@faststreamtech.com

MaxEye Technologies hiring vlsi freshers

MaxEye Technologies hashtag#Hiring hashtag#Freshers for our office in Bangalore and Chennai. We are looking for BE/BTech and ME/MTech freshers ( final year students can also apply for internship+full time job) from ECE and EEE branches. Required Skills: For ECE Branch ------------------- 1. Strong fundamentals in Signal processing and Communication concepts 2. Programming : C and C++ For EEE Branch ------------------- 1. Strong fundamentals in Electrical Machines, Battery, Inverter, Power electronics and Power systems 2. Programming : C and C++ Optional Skills -------------------- 1. Expertise in LabVIEW programming is an advantage Interested candidates please share your profile to harikesh.bs@maxeyetech.com. For more information visit our website www.maxeyetech.com.

Company : maxeyetech Location : bangalore Share Your Resume : harikesh.bs@maxeyetech.com

exiger hiring VLSI freshers

Exiger hiring fresh Engineering graduates (2017/2018 passed out) with excellent academic records and strong VLSI/CMOS fundamentals for IO/Std cell characterization trainee position

Company : exiger Location : bangalore Share Your Resume : career@exiger.co.in

infosys hiring freshers

Infosys empowers you to pursue your ambition and achieve what you desire! Infosys inviting applications from B.E., hashtag#BTech, ME, hashtag#MTech, hashtag#MSc and MCA graduates of 2016, 2017 and 2018 to join them. Apply today at https://infy.com/2QP9C3Q

Company : Infosys Location : bangalore Share Your Resume : https://infy.com/2QP9C3Q

Embedded freshers hiring Graphene Semiconductors services

Embedded freshers hiring Graphene Semiconductors services Qualification: B.E/B.tech/M.E/M.tech Passed out : 2018 only talent@graphsemi.com

Company : graphsemi Location : bangalore Share Your Resume : talent@graphsemi.com

Synopsys hiring IT Interns

Synopsys hiring IT Interns Intern (Technical-IT): Please find the JD below: Operating Systems: Linux, Windows Key Technologies: Machine Learning [ Good to have ] Programming Language: Python [ Necessary ] and C, C++ Areas of Interest: Big data analytics, Operating Systems, Computer Networks, Cryptography Key Requirements: Python Knowledge, Analytical Skills in programming. Job Location: Hyderabad Internship period: 1 Year Experience Level: 0 to 2 Years Connect me at rashmis@synopsys.com / Ph. 040 40331696

Company : synopsys Location : bangalore Share Your Resume : rashmis@synopsys.com

hiring freshers for Verification

Hiring for Verification Engineers !! interested candidates can send me your updated resume to: reshma@blueberrysemi.com walk in date 4th JAN 2019

Company : blueberrysemi Location : Ahemadabad Share Your Resume : reshma@blueberrysemi.com

VLSI freshers hiring at Imgtech

Excellent opportunity for M.Tech / M.S. Freshers (VLSI / Digital Electronics) 2017/18 Passed outs who are looking for IP Verification openings. Desired skills: Job Location: Pune –Designation: Graduate hardware Engineer • An excellent academic record. • An excellent understanding of Digital Electronics fundamentals. • Understanding of VHDL and/or Verilog languages. • Good understanding of OOPs concepts • Who can join in less than 30 days Interested candidates, please share to this email id – Srinivas.kota@imgtec.com

Company : Imgtech Location : pune Share Your Resume : Srinivas.kota@imgtec.com

Syntel hiring freshers

Syntel hiring fresh graduates Only 2018 passouts Criteria: BE / BTECH / MCA : Associate Engineers - Technology @ Chennai / Bangalore / Hyderabad / Pune Criteria: BE/Btech(any)/MCA(2018 batch) (60% through out) Apply from below link http://tests.mettl.com/drive/Syntellect-2018-BE-MCA-Candidate-Registration-Form-OC/?fbclid=IwAR31qUfJQdQ01ispgB7Mhz6VNXs-w-QqJ1XcYKs9ZXmOOcqS3J2AbA-JJDk

Company : syntel Location : bangalore Share Your Resume : na

Opportunity for Physical Design Engineer

xcellent Opportunity for Physical Design Engineer : Location : Bangalore Experience : 0-2 Years Job Description: - Must have completed M. Tech in VLSI - Should have good knowledge of Physical Design Flow - Should be good in one of the scripting language (TCL/Perl/Python) - Must have good digital electronics concepts - Should have good knowledge of STA/Synthesis - Must have good communication and presentation skills - Stipend will be the best in industry Interested share resume to Shubhanshi@siliconplay.com

Company : silicanplay Location : bangalore Share Your Resume : Shubhanshi@siliconplay.com

Syntel hiring fresh graduates

Syntel hiring fresh graduates..!! Only 2018 passouts Criteria: BE / BTECH / MCA : Associate Engineers - Technology @ Chennai / Bangalore / Hyderabad / Pune Criteria: BE/Btech(any)/MCA(2018 batch) (60% through out)

Company : Syntel Location : na Share Your Resume : https://lnkd.in/fyCxfc2

software freshers at modussystems

hiring software Freshers bangalore whose qualification should be hashtag#BE/B. Tech/MCA graduated in 2016/2017/2018. Anyone interested can forward the resume to freshers@modussystems.com. Required skillset :Either SQL, Pl/Sql and Unix or Java /J2EE and unix

Company : modussystems Location : bangalore Share Your Resume : freshers@modussystems.com

VLSI Intern at Synopsys

VLSI Intern at Synopsys

Company : synopsys Location : na Share Your Resume : https://lnkd.in/fbABjEg

ASIC Verification Engineer

Job Profile:ASIC Verification Engineer Qualifications: BE/B.Tech/M.Tech in Electronics and Communication Engineering/VLSI Design Experience: 4+ Years in ASIC Verification Skills Required: • Experience with SV/UVM/OVM/VMM or Specman/eRM/UVMe • Familiarity with scripting languages like Perl, TCL • SVA, assertion based formal verification, Coverage Driven Verification • Experience with SOC with C/ASM based tests, Graphics or CPU is an added advantage • Proficient on protocols – AXI, AHB, USB, PCIe, DDR, LPDDR, HDMI, MIPI, Ethernet. • Should have good debugging skills and strong digital design fundamentals. Job Description: • Develops preSilicon functional validation tests to verify system will meet design requirements. • Creates test plans for RTL validation, defining and running system simulation models, • Work with regression tools and develop scripts to submit cases for regression analysis. • Develop test benches using UVM, automation and create stimulus to verify the design under test • Technical mentoring for junior team members along with execution responsibilities.

Company : Faststream Technologies Location : Bangalore Share Your Resume : ashish.rout@faststreamtech.com

Physical Design Engineer

Experience: 2+ Years in Physical Design Skills Required: • Experience in ASIC Physical Design RTL to GDSII Implementation flow • Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc. • Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal) • Knowledge of Timing .lib generation, Physical View Generation (LEF, GDS, CEL, FRAM, NDM etc.) • Physical Verification (DRC/LVS/Density/Antenna etc.) • Reliability Verification (EM/IR drop etc.) • Well versed with TCL/Perl/Shell Scripting • EDA tool knowledge: Design Compiler, ICC/ICC2, Spectre, Virtuoso, Primetime, ICV Job Description: • Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out • Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification • Multiple Power Domain Analysis using standard Power Formats UPF/CPF

Company : Faststream Technologies Location : Bangalore Share Your Resume : ashish.rout@faststreamtech.com

Physical Design Engineer

Experience: 2+ Years in Physical Design Skills Required: • Experience in ASIC Physical Design RTL to GDSII Implementation flow • Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc. • Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal) • Knowledge of Timing .lib generation, Physical View Generation (LEF, GDS, CEL, FRAM, NDM etc.) • Physical Verification (DRC/LVS/Density/Antenna etc.) • Reliability Verification (EM/IR drop etc.) • Well versed with TCL/Perl/Shell Scripting • EDA tool knowledge: Design Compiler, ICC/ICC2, Spectre, Virtuoso, Primetime, ICV Job Description: • Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out • Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification • Multiple Power Domain Analysis using standard Power Formats UPF/CPF

Company : Faststream Technologies Location : Bangalore Share Your Resume : ashish.rout@faststreamtech.com

ASIC Design Engineer

Experience: 2+ Years in ASIC Design Skills Required: • Strong Hands on experience in Verilog/VHDL/System Verilog for design. • Hands on experience in Linting, Synthesis, Static Timing Analysis and LEC • Should be able to work independently once the design requirements are specified • Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory, OTP, I2C/SPI • Knowledge of VP3, Perl is a plus Job Description: • Responsible for Front-End chip implementation including design integration, synthesis and execution flows that starts with RTL coding and ends with the delivery of a netlist package ready for physical design. • Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management. • Work in collaboration with Physical Design Engineers in chip level planning and integrations. • Interact with verification engineers for test plan review, coverage debug • Technical mentoring for junior team members along with execution responsibilities.

Company : Faststream Technologies Location : Bangalore Share Your Resume : ashish.rout@faststreamtech.com

Analog Design Engineer

Skills Required: • Sound fundamentals in CMOS devices, basics of VLSI design and really good timing concepts involving dynamic and sequential circuits. • Involved in architectural and micro architecture design. • Experience of designs in 28nm,40nm, 65nm, 90nm, 130nm, 0.18um, CMOS technologies. • Experienced in Lint, CDC, logic synthesis, formal verification and static timing analysis. • Knowledge in DFT is must. • Good script language skill using Tcl, Perl. • Experienced with Mixed signal design flow using Cadence Virtuoso, PVS, ASSURA and Calibre tools. Job Description: • Driving system specifications, defining circuit architectures and enabling designs meeting power, performance and cost for next generation optical interconnects. • Specify, architect and design low voltage and low power Mixed-Signal integrated circuits from product definition through characterization and qualification. • Plan design work with constraints on performance, power, time and quality. • Provide guidance to junior designers and layout engineers.

Company : Faststream Technologies Location : Bangalore Share Your Resume : ashish.rout@faststreamtech.com

Opportunity for ASIC Verification Engineer

Excellent Opportunity for Verification Engineer : Location : Noida Experience : 0-2 Years Job Description- - Must have completed M. Tech in VLSI - Should have good knowledge of Verilog/System Verilog - Should be good in OOPS concepts - Must have good digital electronics concepts - Should be familiar with UVM - Must have good communication and presentation skills - Stipend will be the best in industry Interested share resume to Shubhanshi@siliconplay.com

Company : Noida Location : noida Share Your Resume : Shubhanshi@siliconplay.com

hiring VLSI freshers at Open Silicon

hiring VLSI freshers at Open Silicon Location: Bangalore Availability: As soon as possible Skills- C++, Python and Verilog. Interested candidates can share their CV at careers.india@open-silicon.com

Company : Open Silicon Location : bangalore Share Your Resume : careers.india@open-silicon.com

Software interns at microsoft

Microsoft is looking for Software Engineering Summer Interns. Eligibility criteria • Year of graduation: 2020 • CGPA 7 and above • No pending backlogs • Pursuing B.Tech / M.Tech / MS degree in CSE/IT Or Circuit branches (ECE/ EEE/ E&I) OR related quantitative field • Candidate should not have participated in Microsoft’s Intern Hiring process within the last one year If eligible and interested, send your resume to abhi.shah@microsoft.com with the strict Subject Line "Microsoft-Summer-Internship" and add your name, college name and email address to the mail.

Company : microsoft Location : na Share Your Resume : abhi.shah@microsoft.com

Dexcel is hiring Trainee Engineers for our Validation Team

Dexcel is hiring Trainee Engineers for our Validation Team. Qualification: Any Graduate in electronics OR Diploma in Electronics Location: Bangalore Write to talent.acquisition@dexceldesigns.com

Company : dexceldesigns Location : bangalore Share Your Resume : talent.acquisition@dexceldesigns.com

SkandySys is hiring for Physical

SkandySys is hiring for Physical Design freshers for Bangalore location , Below is the JD 1. Basics of CMOS circuits 2. Digital Design Concepts 3. Analytical skills 4. Communication Interested candidates can share profile to rekha.g@skandysys.com

Company : skandysys Location : bangalore Share Your Resume : rekha.g@skandysys.com

ASIC Verification Engr freshers at frenustech

Hiring ASIC SoC SV, UVM Verification Trained freshers, We are conducting a hiring drive yet again this week. Interested, Pls share CV asap.

Company : frenustech Location : bangalore Share Your Resume : Deven.kr@frenustech.com

DFT Engineer

DFT Engineers: Requirement for DFT Engineers. Requirements: • Experience: 4 – 10 Years • Work Location : Bangalore / Onsite. Job Description: • Professionals are expected to have good hands-on experience in the following areas: • Complete understanding of DFT concepts and flow (ATPG/Memory BIST//Logic BIST/Scan insertion & Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing) on complex SOCs to improve testability. • Familiarity of any one of the tools (DFT Compiler/RTL Compiler, Testkompress/Tetramax, Virage/Mentor memory BIST, Mentor Bscan) • Test coverage analysis, optimization, Patter Generation/ conversion/ simulation, Time Closure, Area, Power, Performance, Synthesis, STA, Route, Floor Plan, Tester Application Time, and Test Data Volume. • Good scripting skills TCL/Perl/Python Interested Professionals with minimum of 4 years of experience can send their Updated profiles to careers@savvychip.com

Company : Savvychip Technologies Location : India / Onsite Share Your Resume : careers@savvychip.com

Application Engineer job opening at Synopsys

Application Engineer job opening at Synopsys, Noida Experience: 1 year or M.tech with Intern experience in timing, synthesis, formality, LEC, formal verification can also apply. Interested candidates mail your resume to akpv@synopsys.com

Company : synopsys Location : noida Share Your Resume : akpv@synopsys.com

VLSI Design Engineers

TEST AND VERIFICATION SOLUTION!!! Our company has urgent opening for following requirement Design Engineer Job Title : Design Engineer Job Description : • General logic design concepts and experience in FPGA logic design • Experience in STA/Synthesis • Synthesis experience for Timing closure • Experience in using TCL/Perl. Basic Job Deliverable : • Should be able to analyze the timing failures, CDC and lint issues. • Should be able to understand the TCL files and strong debugging skills is desired. Qualification : Bachelor’s/Master’s in ECE Experience Level : 1-2 Expected hire date : 10th Dec, 2018 Expected hire duration : 1-2 years Total Experience: - 1 Years to 2Years No. of Positions: 6 Location: Hyderabad Notice period – LESS THEN 15DAYS Those who are interested can forward their resumes to bhagyalakshmi.m@testandverification.com or call 08033451855

Company : TEST AND VERIFICATION SOLUTION Location : bangalore Share Your Resume : bhagyalakshmi.m@testandverification.com

TCS recruitment drive

TCS recruitment drive 2017/2018 passed out : Registration end date: 9th Dec, 2018 Hall ticket issue date: 12th Dec, 2018 Date of test : 16th Dec, 2018 Join TCS : Jan 1st week onwards Registration Link : https://lnkd.in/fkp5KKU Registration open to all engineering stream ! TCS Off Campus Drive - Batch of 2017 and 2018 is a Pan India drive followed by a personal interview process. Post the assessment, interview date and location will be communicated to candidates individually. Year Of Passing : Batch of 2017 and 2018 Compensation : 3.36 L PA for B.E / B.Tech 3.53 L PA for M.E / M.Tech / MCA / M.Sc Test Pattern for TCS Off Campus Assessment: Sections: Verbal Ability -10 mins (questions -10) Quantitative Aptitude - 40 mins (questions -20) Programming Concepts - 20 mins (questions -10) Coding - 20 mins (questions -1)

Company : tcs Location : Hyderabad Share Your Resume : Registration Link : https://lnkd.in/fkp5KKU

VLSI Intern at Synopsys

hashtag#JobDescription: Responsible for developing, applying, and maintaining quality standards for company products. Develops and executes software test plans. Analyzes and writes test standards and procedures. Maintains documentation of test results to assist in debugging and modification of software. Analyzes test results to ensure existing functionality and recommends corrective action. BU Specific Role & Responsibilities: •Functional testing of ARC Processor Products (release candidates) in embedded HW and SW area •Global team communication and collaboration including, but not limiting to processor cores, subsystems, operating systems, multimedia software and development boards teams The criteria is BTech EC/EE/CSE with good grades. Good to have embedded/VLSI knowledge and willing to work in testing team Interested? Please share your CV to rashmis@synopsys.com Ph 040 40331696

Company : synopsys Location : Hyderabad Share Your Resume : rashmis@synopsys.com