VLSI Job Seekers :: VLSI Training Institute in Bangalore

ASIC Verification Engr freshers at frenustech

Hiring ASIC SoC SV, UVM Verification Trained freshers, We are conducting a hiring drive yet again this week. Interested, Pls share CV asap.

Company : frenustech Location : bangalore Share Your Resume : Deven.kr@frenustech.com

DFT Engineer

DFT Engineers: Requirement for DFT Engineers. Requirements: • Experience: 4 – 10 Years • Work Location : Bangalore / Onsite. Job Description: • Professionals are expected to have good hands-on experience in the following areas: • Complete understanding of DFT concepts and flow (ATPG/Memory BIST//Logic BIST/Scan insertion & Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing) on complex SOCs to improve testability. • Familiarity of any one of the tools (DFT Compiler/RTL Compiler, Testkompress/Tetramax, Virage/Mentor memory BIST, Mentor Bscan) • Test coverage analysis, optimization, Patter Generation/ conversion/ simulation, Time Closure, Area, Power, Performance, Synthesis, STA, Route, Floor Plan, Tester Application Time, and Test Data Volume. • Good scripting skills TCL/Perl/Python Interested Professionals with minimum of 4 years of experience can send their Updated profiles to careers@savvychip.com

Company : Savvychip Technologies Location : India / Onsite Share Your Resume : careers@savvychip.com

Application Engineer job opening at Synopsys

Application Engineer job opening at Synopsys, Noida Experience: 1 year or M.tech with Intern experience in timing, synthesis, formality, LEC, formal verification can also apply. Interested candidates mail your resume to akpv@synopsys.com

Company : synopsys Location : noida Share Your Resume : akpv@synopsys.com

VLSI Design Engineers

TEST AND VERIFICATION SOLUTION!!! Our company has urgent opening for following requirement Design Engineer Job Title : Design Engineer Job Description : • General logic design concepts and experience in FPGA logic design • Experience in STA/Synthesis • Synthesis experience for Timing closure • Experience in using TCL/Perl. Basic Job Deliverable : • Should be able to analyze the timing failures, CDC and lint issues. • Should be able to understand the TCL files and strong debugging skills is desired. Qualification : Bachelor’s/Master’s in ECE Experience Level : 1-2 Expected hire date : 10th Dec, 2018 Expected hire duration : 1-2 years Total Experience: - 1 Years to 2Years No. of Positions: 6 Location: Hyderabad Notice period – LESS THEN 15DAYS Those who are interested can forward their resumes to bhagyalakshmi.m@testandverification.com or call 08033451855

Company : TEST AND VERIFICATION SOLUTION Location : bangalore Share Your Resume : bhagyalakshmi.m@testandverification.com

TCS recruitment drive

TCS recruitment drive 2017/2018 passed out : Registration end date: 9th Dec, 2018 Hall ticket issue date: 12th Dec, 2018 Date of test : 16th Dec, 2018 Join TCS : Jan 1st week onwards Registration Link : https://lnkd.in/fkp5KKU Registration open to all engineering stream ! TCS Off Campus Drive - Batch of 2017 and 2018 is a Pan India drive followed by a personal interview process. Post the assessment, interview date and location will be communicated to candidates individually. Year Of Passing : Batch of 2017 and 2018 Compensation : 3.36 L PA for B.E / B.Tech 3.53 L PA for M.E / M.Tech / MCA / M.Sc Test Pattern for TCS Off Campus Assessment: Sections: Verbal Ability -10 mins (questions -10) Quantitative Aptitude - 40 mins (questions -20) Programming Concepts - 20 mins (questions -10) Coding - 20 mins (questions -1)

Company : tcs Location : Hyderabad Share Your Resume : Registration Link : https://lnkd.in/fkp5KKU

VLSI Intern at Synopsys

hashtag#JobDescription: Responsible for developing, applying, and maintaining quality standards for company products. Develops and executes software test plans. Analyzes and writes test standards and procedures. Maintains documentation of test results to assist in debugging and modification of software. Analyzes test results to ensure existing functionality and recommends corrective action. BU Specific Role & Responsibilities: •Functional testing of ARC Processor Products (release candidates) in embedded HW and SW area •Global team communication and collaboration including, but not limiting to processor cores, subsystems, operating systems, multimedia software and development boards teams The criteria is BTech EC/EE/CSE with good grades. Good to have embedded/VLSI knowledge and willing to work in testing team Interested? Please share your CV to rashmis@synopsys.com Ph 040 40331696

Company : synopsys Location : Hyderabad Share Your Resume : rashmis@synopsys.com