VLSI Job Seekers

PD Fresher Drive at Whizchip

Conducting PD Fresher Drive @ Whizchip, Bangalore on 26th Sep(Wednesday), who has completed their "Physical Design" can apply and share their updated CV ASAP to annapurnabm@whizchip.com Interview process will be Written Test followed the technical discussion

Company : whizchip Location : bangalore Share Your Resume : annapurnabm@whizchip.com

Memory Design Memory Layout Freshers

Memory Design / Memory Layout Freshers & Juniors Criteria • 2017 or 2018 Passed out • 70% or Above in Academics • Completed training in some training Institute • Must be available for F2F interview in Weekdays Deepak.jaishankar@insemitech.com

Company : Insemi Location : bangalore Share Your Resume : Deepak.jaishankar@insemitech.com

Physical Design Engineer

Will be responsible for implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Python etc Must have good communication & problem solving skills. Should be able to handle PnR tasks with minimal supervision Bachelor/Master Degree in Electronics Engineering. Desirable Design Experience in: 1. SoC implementation expertise. Multimillion gates integration. 2. Physical Synthesis, Constraints validation. 3. Floor planning, Power planning. 4. Clock Tree Synthesis (CTS). 5. Scan Synthesis, Scan re-order.

Company : Juntran Technologies Pvt Ltd Location : Bangalore Share Your Resume : hr@juntrantech.com

Mega Drive for Physical Design Trained freshers at junTran

Mega Drive for Physical Design Trained freshers at junTran Mega -Recruitment -Drive - On - 16th September 2018 - Conducting by junTran Technolosies pvt Ltd Timing : 10.00 AM to 11.30 AV V Avenue :- Conference Hall, 5th floor, SiriKudam Appartment, Kasavanahalli, Sarjapura Road, Bangalore. Contact no : 9741642042

Company : junTran Location : bangalore Share Your Resume : na

PD trained freshers hiring at digicomm

Hiring PD trained freshers for Pune Location, interested please share me your cv to shivaranjini@digicomm.org

Company : digicomm Location : pune Share Your Resume : shivaranjini@digicomm.org

Freshers Hiring Analog Design at tessolve

Freshers Hiring Analog Design We are hiring freshers / trained engineers for the below requirements: • Analog Layout • Analog Design • AMS Verification Eligibility to apply : • B.Tech/M.Tech (E&C) 2017/2018 passed out with 70% above • Trained from reputed institutes are preferred Interview process for fresher hire : 1) Sunday, 16th Sep’18 - Written test 2) Saturday, 22nd Sep’18 - Technical Interview, HR Interview Please send to analogvlsi-hr@tessolve.com OR vlsi_staff@tessolve.com

Company : tessolve Location : bangalore Share Your Resume : analogvlsi-hr@tessolve.com

Hiring Junior ASIC Verification engineers

Hiring Junior ASIC Verification engineers Experience: 0.6 - 1 years Location: Bangalore Eligibility: M.Tech VLSI Selection process: Written Test/Interview Note: Only Shortlisted candidates will get interview call Please share your updated resumes to fresher@radiantsemi.com

Company : radiantsemi Location : bangalore Share Your Resume : fresher@radiantsemi.com

hiring VLSI interns at SYNOPSYS

ntern (Technical-Engineering) 16836BR INDIA - Hyderabad Job Description and Requirements Responsible for developing, applying, and maintaining quality standards for company products. Develops and executes software test plans. Analyzes and writes test standards and procedures. Maintains documentation of test results to assist in debugging and modification of software. Analyzes test results to ensure existing functionality and recommends corrective action. BU Specific Role &Responsibilities: •Functional testing of ARC Processor Products (release candidates) in embedded HW and SW area •Global team communication and collaboration including, but not limiting to processor cores, subsystems, operating systems, multimedia software and development boards teams •Evaluate out-of-the-box user experience according to pre-defined product release timeline •Interoperability testing of product dependencies to ensure integrity of company portfolio •Verification of product documentation •Product test automation (As and when needed) •Communication with development, QA and corporate application engineers to ensure high quality of products

Company : synopsys Location : Hyderabad Share Your Resume : https://sjobs.brassring.com/TGnewUI/Search/home/HomeWithPreLoad?PageType=JobDetails&jobId=136172

Samsung Semiconductor is Hiring DV Engineer

Samsung Semiconductor is Hiring DV Engineer for Bangalore Location 3-12+ Years of Expertise on SV-UVM worked on IP or Sub-System or System level verification. Interested Professional can share your updated Profile to k.swetha@partner.samsung.com

Company : samsung Location : bangalore Share Your Resume : k.swetha@partner.samsung.com

Cadence is Hiring for Freshers Physical Design

Cadence is Hiring for Freshers : Physical Design Field Application Engineer B.E/B,Tech/M.Tech ECE,EIE,EEE,VLSI passout from Tier I college with above 80% or 8 CGPA across academics students can apply. Interview Date : 8 Sept 2018 Location : Bangalore Interested students should be available for written test & technical interview at our campus. Please share your resume @ chetanb@cadence.com

Company : cadence Location : bangalore Share Your Resume : chetanb@cadence.com

nvidia hiring fresher and Exp

Job opening at nvidia graphics in DFT (VLSI) for fresher and exp candidate at Bangalore and Hyderabad location. Please send resume to sraj@nvidia.com also mention preferred location.

Company : nvidia Location : pan india Share Your Resume : sraj@nvidia.com

SmartSoC Solutions hiring freshers for Verification Engineer

SmartSoC Solutions hiring freshers for Verification Engineer Role. interested Candidates kindly share cv to nandini.g@smartsocs.com

Company : smartsocs Location : bangalore Share Your Resume : nandini.g@smartsocs.com

hindujatech hiring VLSI freshers

hindujatech hiring VLSI freshers Qualification M.E,M.Tech 2018 passouts only Specialization EEE, Embedded, Power Electronics, VLSI and Mechatronics Job Location Chennai Share resumes to the below ID with the Subject line ME,M.tech2018 Passout only to abilash.srinivasan@hindujatech.com

Company : hindujatech Location : chennai Share Your Resume : abilash.srinivasan@hindujatech.com

blueberyysemi hiring fresher for analog layout engineers

blueberyysemi hiring fresher for analog layout trained analog layout engineers experience: should have undergone 6 months training period(minimum) if interested please send me your updated resume to: reshma@blueberyysemi.com

Company : blueberyysemi Location : bangalore Share Your Resume : reshma@blueberyysemi.com

VLSI Fresher Walk in Interview at SiValley Technologies

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Company : SiValley Technologies Location : bangalore Share Your Resume : na

hiring fresher forVerification Engineering at mentor graphics

hiring fresher for ASIC Verification Engineering at mentor graphics ASIC verification Engineering profile. share your CV - tanu_shri@mentor.com Work location - Noida Wxp - 0 to 1 year (2017, 2018 passed out) Education - B.Tech/ M.Tech (Electronics) from IIT/ NIT/ NSIT/ DCE/ Thapar/ Jadavpur etc premium colleges only. If you are interested, please revert with your CV ASAP.

Company : mentor graphics Location : noida Share Your Resume : tanu_shri@mentor.com

VLSI Freshers WALK in at VVDN

VLSI Freshers WALK-IN at VVDN VVDN is conducting a walk-in drive for the positiontof RTL Design Engineer on 28 August 2018, Tuesday. Job location : Kochi Qualification : BE/B.Tech/ME/M.Tech 1111 or equivalent in ECE/EEE Interview process ■ Written Test ■ Technical Interview ■ HR Round Reporting time 09:00 AM Interested candidates please drop a mail to amrutha.m@vvdntech.in VVDN TECHNOLOGIES Venue : VVDN Technologies Pvt Ltd, 215A, Michel Tower, Civil Lane Road, Padamugal junction, Thrikkakara, P.0, Kakkanad, Kochi, Kerala 682021

Company : VVDN Location : Kochi Share Your Resume : amrutha.m@vvdntech.in

InSemi hiring

InSemi hiring "Memory Design Trained freshers" OR "Memory Design Intern" If you are interested in this opportunity please share me your profile to : santhosh.ajayakumar@insemitech.com

Company : insemi Location : bangalore Share Your Resume : santhosh.ajayakumar@insemitech.com

Graphene semiconductor hiring fresher

Graphene semiconductor hiring for B.Tech(Electronics and Communication)/ M.Tech in Computer Science/E&C ) #2017 & #2018 pass outs (Colleges in Bangalore Approved by AICTE ) for Trainee Engineer. hashtag#location-Bangalore If you are interested or if you know someone who is interested can drop their resumes at padmini.v@graphsemi.com

Company : graphsemi Location : bangalore Share Your Resume : padmini.v@graphsemi.com

Intern opportunities at Intel

Job Type: Intern Intern Job Description Creates, defines and develops system validation environment and test suites. Uses and applies emulation and platform-level tools and techniques to ensure performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features. Qualifications B.E/M.E/M.Tech. in Electrical ElectronicsCommunicationSoftwareComputer Science Engineering with above 75% or 8 CGPA. Interest towards working with group of top notch Bluetooth/WiFi Validation team and grow as a key Validation System Engineer.Excellent C++/C programming and Python/Perl test scripts development. Debug flows and writing test cases to the specification. Windows/Linux/Chrome systems understanding. Have an advantage if the candidate has Good understanding of Bluetooth or WiFi communication protocol knowledge and Deep OS internals knowledge

Company : Intel Location : bangalore Share Your Resume : https://jobs.intel.com/ShowJob/Id/1745567/Intern

hiring fresher physical design engg

Si2Chip is hiring for Physical Design Trained Freshers for Bangalore location. interested can share share your updated CV @ himanshu.pandey@si2chip.com

Company : si2chip Location : bangalore Share Your Resume : himanshu.pandey@si2chip.com

Synopsys hiring VLSI Internships positions

PhysicalDesign - Technical Intern position open at Synopsys Inc for hashtag#Hyderabad Location. Min Qualification - Btech/ Mtech in VLSI Design Trained candidates on PD are preferred Interested Folks - please share your CVs to rashmis@synopsys.com Ph. 040 40331696

Company : Synopsys Location : Hyderabad Share Your Resume : rashmis@synopsys.com

Synopsys hiring VLSI Internships positions

Physical design Internship opportunity for 1 year at Synopsys, Bangalore. M.tech VLSI 2018/2019 are eligible. B.tech/M.tech Physical design trained freshers can also apply. Note: Interview for shortlisted candidates will be held in Synopsys, Noida office next week. Those who have attended the PD Internship drive at Synopsys Bangalore and Hyderabad offices earlier are not eligible. Kindly share profiles at akpv@synopsys.com

Company : synopsys Location : Noida Share Your Resume : akpv@synopsys.com

blueberrysemi hiring VLSI freshers

6+ months experience, SV-UVM trained verification engineers, Good in verification basics, communication, ability to learn fast, dynamic/proactive, passionate to make career in verification If you are interested or if you know someone who is interested can drop their resumes to Naveen.yk@blueberrysemi.com

Company : blueberrysemi Location : bangalore Share Your Resume : Naveen.yk@blueberrysemi.com

RealSilicon hiring for VLSI Fresher

RealSilicon Bangalore is looking for B.Tech/M.Tech trained RTL/Verif candidates. If you are having the matching skill set. Please mail your updated resume at – careers@realsilicon.com

Company : realsilicon Location : BANGALORE Share Your Resume : careers@realsilicon.com

ASIC verifiction jobs at ignitarium

ignitarium conducting a weekend drive this Saturday (4th Aug 2018) at Ignitarium Kochi office. Eligibility: B Tech/M Tech with min 1 year exp in Design Verification/ SoC Verification/FPGA Design Please rush your referrals to careers@ignitarium.com. Shortlisted candidates will be contacted by the staffing team with an appointment.

Company : ignitarium Location : Kochi kerala Share Your Resume : careers@ignitarium.com

Wipro Hiring Freshers

Education 10th Standard: 60% or above 12th Standard: 60% or above Graduation: 60% or above OR minimum 6.00 CGPA OR Equivalent (as applicable by the university guidelines) Year of Passing 2018 Qualification B.E./B.Tech. Branch of Study CS/ IT/ ECE/ EEE/ E&I/ Mechanical/ Automobile/ Production Engineering/ Aeronautical/ Mechatronics Designation Project Engineer Compensation Salary: INR 3.20 or 3.30 lacs per annum Service Agreement Applicable for 15 months post joining @ INR 75,000 on pro rata basis Other Criteria Should be from a Full-time Degree course recognized by the Central/State Government of India. All Arrears and backlogs need to be cleared at the time of selection process. Should have completed all exams/ viva-voice/ training and should not have any pending attendance requirement with the college.

Company : Wipro Location : BANGALORE Share Your Resume : https://careers.wipro.com/campus-engineering.aspx

Dexcel is hiring for Trainee FPGA Engineers

Dexcel is hiring for Trainee FPGA Engineers. Criteria: M.E/ M.Tech (VLSI), Trained in VLSI from reputed institutes. Send profiles to talent.acquisition@dexceldesigns.com Availability: Immediate

Company : dexceldesigns Location : BANGALORE Share Your Resume : talent.acquisition@dexceldesigns.com

Senior Design Verification Engineer

Job Description: · 2 to 12 years of experience in Verification · Design and develop test benches using HVLs like System Verilog · Deep expertise in Verification Methodologies like UVM, OVM, VMM · Knowledge of ARM based SOC verification / Interface protocols like PCIe, MIPI, PHY, USB, SATA/SOC verification is essential · Should have experience in creating test plans, Ethernet

Company : Cerium Systems Location : Bangalore,Kochi & Vishakapatnam Share Your Resume : bhanu.chinnareddy@cerium-systems.com

Synopsys hiring VLSI Freshers

Applications Engineer 18658BR INDIA - Hyderabad Job Description and Requirements Synopsys IC Validator (ICV) is a comprehensive signoff DRC / LVS tool architected and proven for In-Design physical verification at leading-edge process nodes. It delivers excellent scalability, superior ease-of-use for the physical designer, and high programmability for easier runset development. The employee would be working on development, qualification and optimization of advanced technology runsets. With the advent of technology, the PV requirements have become very complex. As a result, the number of checks in runsets have increased multi-fold and warrant fairly challenging coding to meet the foundry requirements. The job requires engineer to develop high quality high performance runsets, which enable Synopsys customers to validate their advanced technology chips for their manufacturability. Development of a runset involves visualization of hierarchical geometries and coming up with creative solutions to meet the design manual expectations. The quality of the runset is ensured by validating it against a specially designed regression suite whose qualification is a pre-requisite before the runset can be released for production use. The engineer is also expected to understand any new technology requirements which are currently not supported by the tool and work with R&D and CAE teams to define clear requirements for them. The job also involves handling customer issues which may require debugging runset issues on full chip designs. Requirements: Person should have B. Tech/M.Tech/MS degree in Electronics/VLSI domain. Should have understanding and exposure to transistor CMOS layouts. A strong understanding of ASIC design flow, VLSI, and/or CAD engineering is desired and knowledge of Perl/Tcl, Unix is a plus. Experience with Physical Verification EDA tool products like Calibre/Assura/Quartz and product knowledge in any of the areas of like writing foundry decks ( DRC/LVS/ERC/DFM), solving LVS issues, knowledge of foundry processes, understanding of cutting edge DFM requirements are highly desired. Job CategoryEngineering Hire Type Employee

Company : Synopsys Location : hydarabad Share Your Resume : https://sjobs.brassring.com/TGnewUI/Search/home/HomeWithPreLoad?PageType=JobDetails&jobId=139741

fresher Physical Design and Analog layout

signoffsemi hiring for Physical Design & Analog Layout Openings. Recent college graduates can apply (BE - EC, EE / Mtech - VLSI only)

Company : signoffsemi Location : BANGALORE Share Your Resume : http://www.signoffsemi.com/entry-level-job-openings/

sarvakarmas hiring ASIC Verification engineers

sarvakarmas recruiting design verification engineers with 6months to 1 year experience to further enhance their knowledge in IP verification (SV UVM based ) and SOC verification. Interested candidates can send their profiles to info@sarvakarmas.com or manjula.k@sarvakarmas.com

Company : sarvakarmas Location : BANGALORE Share Your Resume : manjula.k@sarvakarmas.com

ON Semi is hiring INTERNS

ON Semi, Bangalore is hiring INTERNS (Test Engineering) only M.Tech Freshers, if you are interested please share your updated resume 1 Bhulakshmi.tankasala@onsemi.com

Company : onsemi Location : BANGALORE Share Your Resume : Bhulakshmi.tankasala@onsemi.com

Job Requirements at Waferspace

Looking for passionate engineers Skills Physical Design Design Verification DFT STA RTL Design

Company : Wafer Space Semiconductors Location : Bangalore Share Your Resume : eswarig@waferspace.com

VLSI Walkin for Freshers at Tesolve

Walkin for Freshers — BE/B.Tech (ECE,ECE) — 10th Aug 2018 Designation: Test Engineer Eligibility: BE/B.Tech : Electrical & Electronics Engineering (EEE), Electronics & Communication Engineering(ECE) Year of Passing : 2017 and 2018 Cut-off Percentage: 65% Last Date for registration: 2nd Aug 2018 Job Location: Bangalore Job Type: Full Time Job Role: • ATE based testing (Verigy/Advantest, Teradyne/Eagle, any other testers including custom made testers) • Bench testing — TestStand, LabView tools • Hardware design engineer — Board design (Digital, Mixed signal, RF) • Application engineer in ATE • FPGA testing using JTAG/BoundaryScan • System level testing • Embedded testing & debugging Skills : • Good in basics of Electrical and Electronics Concepts, Good communication skills and go getter attitude. • Should have good analytical and problem solving skills, ability to express new ideas, interpersonal skills

Company : tessolve Location : BANGALORE Share Your Resume : http://hris.tessolve.com/walkin/

ASIC RTL verification Engineer at mirafra

looking for female candidates with 0-1 year of experience working on ASIC RTL. Any projects done during graduation,post graduation related to ASIC RTL will also work.Please share CVs at anushikakoul@mirafra.com

Company : mirafra Location : BANGALORE Share Your Resume : anushikakoul@mirafra.com

Qualcomm is looking for VLSI freshers

Qualcomm is looking for freshers and experience candidates for software and VLSI domain. Interested candidates can share profile along with job ID on gaujai@qti.qualcomm.com

Company : qualcomm Location : BANGALORE Share Your Resume : gaujai@qti.qualcomm.com

Modeling Intern

Hiring a Python/Matlab modeling intern - Ideally a fresh CompSci/ECE Bachelor or Master graduate having a good mix of research and hacker genes!

Company : PeakSense Technologies Location : Bangalore India Share Your Resume : hr@peaksense.in

VLSI Freshers hiring for MemoryLayoutEngineers at pozibility

hiring for MemoryLayoutEngineers for 1-4 Years of Relevant #Experience Note : #Trained #candidates if interested then share your resume and if your shortlisted then i will get back to you on 10-07-2018. Location: Bangalore. Walk-in on 11-07-2018 @11 AM Walk-in address: #3, 4th crosss Near Jaya Paradise arpartment, govindappa lane, kodihalli, bangalore-560008 please feel free to contact if you need any further information and share your resumes to kala@pozibility.in

Company : pozibility Location : BANGALORE Share Your Resume : kala@pozibility.in

Physical design Internship opportunity at synopsys

Physical design Internship opportunity for 1 year at Synopsys, Bangalore. M.tech VLSI 2018/2019 are eligible. Kindly share profiles at akpv@synopsys.com B.tech/M.tech Trained Physical design freshers can also apply.

Company : synopsys Location : BANGALORE Share Your Resume : akpv@synopsys.com

Hiring Verification Engineers

· Minimum 2.5 years of ASIC/SOC Verification experience · Experienced in System Verilog and any methodologies OVM/UVM · Experienced in one or two protocols like DDR, PCI-E, USB, SATA, MIPI, Ethernet · Added advantage if exposed to CPU based SoC Verification · Experienced in Assertions and coverage

Company : Eximius Design Location : Bangalore Share Your Resume : balachowdaiahp@eximiusdesign.com

hiring vlsi fresher for Analog Layout Freshers at Ensilica

looking out for Trained Analog Layout Freshers, Interested Job aspirants can reach us at careers.india@ensilica.com with the latest resume.

Company : ensilica Location : BANGALORE Share Your Resume : careers.india@ensilica.com

Cadence is Hiring for Freshers for Intern position

Cadence is Hiring for Freshers : Intern position Layout Engineer B.E/B,Tech (EC) passout with above 75% or 7.5 CGPA across academics. Location : Bangalore Interview Date : 11 July 2018, Bangalore Shortlisted candidates will get email from me with venue details. We will pay monthly 18 to 19K, after one year you will be converted depending on your performance. Interested students should be available for written test in next week at our campus. Please share your resume @ chetanb@cadence.com

Company : cadence Location : BANGALORE Share Your Resume : chetanb@cadence.com

freshers hiring for Design and Verification

Looking for Design and Verification Trained Freshers - 2017 / 2018 Passout - MTech only. Share updated resume @ veena.patil@si2chip.com.

Company : si2chip Location : BANGALORE Share Your Resume : veena.patil@si2chip.com

Altran conducting recruitment drive for ASIC Verification for Freshers

conducting recruitment drive for ASIC Verification Freshers Saturday, 7 July 2018 @ Pritech Office Eligibility Criteria Candidates must be trained in ASIC Verification domain B.E/B.Tech/M.E/M.Tech in EE/EC — 2016/2017 Passout (Interns are eligible) Should have secured 70`15 & above throughout academics Share your referrals to employee,referral@altran.com

Company : altran Location : BANGALORE Share Your Resume : employee,referral@altran.com

Verification Manager

We have opening for for our Verification Team. ODC Project. Skill and Number of Positions : 1. Technical Manager : 10+Yrs Exp ( 1-Positions ) 2. Project Leader : 8+ Yrs Exp ( 1-Positions ) 3. Lead Engineer : 6+Yrs Exp ( 2-Positions ) 4. Senior Engineer : 3+ Yrs Exp ( 4-Positions ) 5. Junior Engineer : 1-3 Yrs Exp ( 6-Positions ) Experience in IP/SOC Verification. Strong Experience in : SV and UVM.

Company : Rakiya Information Technology Solution Location : Bangalore Share Your Resume : rekha@rakiyaworld.com

PHYSICAL DESIGN

 Candidate should have very good experience in complete PnR and Signoff tasks including Floor planning, Placement, CTS, routing, post route optimization, STA closure, Physical verification and power analysis.  Candidate should have worked in multiple Tapeouts. The experience in 16nm and lower nodes is an added advantage.  Candidate should have good knowledge in scripting languages like TCL and PERL.  Candidate will be responsible for executing PNR tasks of the blocks and or full chip activities and also he needs to help couple of junior members in the team whenever they need some help.  We have technical and Managerial ladder for the candidates and as an organization we will help the candidate to identity and grow either in technical ladder or Managerial ladder based on the candidates skill set and the interest.

Company : Cientra Tech Solution (Formerly Mindlance Technologies) Location : Bangalore Share Your Resume : sangeetha.amin0508@mindlancetech.com

PHYSICAL DESIGN

 Candidate should have very good experience in complete PnR and Signoff tasks including Floor planning, Placement, CTS, routing, post route optimization, STA closure, Physical verification and power analysis.  Candidate should have worked in multiple Tapeouts. The experience in 16nm and lower nodes is an added advantage.  Candidate should have good knowledge in scripting languages like TCL and PERL.  Candidate will be responsible for executing PNR tasks of the blocks and or full chip activities and also he needs to help couple of junior members in the team whenever they need some help.  We have technical and Managerial ladder for the candidates and as an organization we will help the candidate to identity and grow either in technical ladder or Managerial ladder based on the candidates skill set and the interest.

Company : Cientra Tech Solution (Formerly Mindlance Technologies) Location : Bangalore Share Your Resume : sangeetha.amin0508@mindlancetech.com

Physical Design Enginner

Implementation / physical design / Electrical Analysis / Macro design hands on working exposure to Synthesis and Compiler, IC Compiler , Z Route, Timing using PT/PTSI, Physical verification. Should have gone through one or more tape outs in 40nm and beyond. Electrical Analysis including Em/IR (Apache), Signal EM, Noise analysis (PTSI-Noise). Scripting using PERL, TCL,with more placement and routing experience.

Company : SmartSoC Solutions Pvt Ltd Location : Bangalore & Hyderabad Share Your Resume : naganandini.bg@smartsocs.com

Analog Circuit Design Engineer

ELVEEGO Circuits hiring for Analog Circuit Design Engineer. Experience: 3-6 Years Work Location: Bangalore and Japan Salary: As per company standards Job Description: 3 to 8 years of relevant experience in Analog circuit designing. Strong experience of designing PLLs, DLLs, ADCs, DACs, SerDes, Analog blocks in technology nodes 16nm, 28nm, 180nm ect., Strong knowledge of CMOS Device

Company : ELVEEGO Circuits Location : 2nd Sector, HSR Layout Bangalore Share Your Resume : geeta.sk@elveegocircuits.com

Hiring Freshers for Verification

BE or ME(Internship + Job) Freshers for Verification Domain (3 Year Bond) Mail Your Resume to mili.shah@softnautics.com , ronak.pandya@softnautics.com , devang.patil@softnautics.com , hr@softnautics.com

Company : SoftNautics LLP Location : Ahmedabad Share Your Resume : mili.shah@softnautics.com , ronak.pandya@softnautics.com , devang.patil@softnautics.com , hr@softnau

Hiring Senior Physical Design Engineer

HIRING Physical Design Engineers - Apply on career@perfectvips.com now! Please see the Job Description below for multiple positions of Physical Design Engineer with total 4 to 9+ years’ experience, with PerfectVIPs Techno Solutions Pvt. Ltd. IN. Location: Bengaluru / Ahmedabad / Onsite in India Education: BE/ ME/ B.Tech/ M.Tech/ MS We also sponsor US Visa! Job Description: Physical Design Engineer Take complete ownership for implementation of Block level designs Responsible for planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below. Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM) Well versed with the level timing closure (STA), timing closure methodologies. Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence.

Company : PerfectVIPs Location : Location: Bengaluru / Ahmedabad / Noida / Pune / Hyderabad / Onsite in India Share Your Resume : career@perfectvips.com

Hiring Senior ASIC Verification Engineer

Hiring Verification Engineers - Apply on career@perfectvips.com now! Please see the Job Description below for multiple positions of Verification Engineer/Senior Verification Engineer/Team Lead with total 3 to 9+ years’ experience, with PerfectVIPs Techno Solutions Pvt. Ltd. IN. Job Description: Location: Bengaluru / Ahmedabad / Noida / Pune / Hyderabad / Onsite in India Experience: 3 – 9 Years & above Education: BE/ ME/ B.Tech/ M.Tech/ MS Responsibilities: · Work as part of a dynamic, motivated, hardworking team · Leading the verification team delivering end to end verification, handling block and full-chip verification of complex SoCs. · Your responsibilities may include Verification environment development, Test cases development, Function and code Coverage Analysis, software integration, etc. · You may also work on Verification IP development or IP Verification activities. Technical Skills Required: · Strong technical fundamentals with superior analytical and problem solving skills, familiarity with OOPs and scripting languages. · Very strong proficiency in HVLs and HDLs (SystemVerilog, Verilog, VHDL, etc.). · Prior expertise with OVM/UVM based test bench with assertion is a big plus. · Working experience in functional coverage and constrained random testing. · Expertise in verification of protocols like Ethernet, PCIe, SATA, USB, SAS, DDR, etc. · ARM based SoC verification is a big plus. · Good communication skills, both written and oral.

Company : PerfectVIPs Location : Location: Bengaluru / Ahmedabad / Noida / Pune / Hyderabad / Onsite in India Share Your Resume : career@perfectvips.com

Verifworks hiring VLSI Freshers

Greetings from VerifWorks Pvt.Ltd. Openings for Design Verification Engineer. Skills : Verilog, System Verilog, UVM,(Mandatory skills) If interested Please share relevant 2015-2016 passed outs with 75% rience:Freshers& 1+ yea Walkin on 30 06 2018 Interested can share profiles to rakshith@verifworks.com contact : 96207444172

Company : verifworks Location : Bengaluru Share Your Resume : rakshith@verifworks.com

InSemi Technology hiring VLSI Freshers

Greetings From InSemi Technology !! We Have openings for : "Memory Layout Trained freshers" "Memory Design Trained Freshers" If you are interested in this opportunity please share me your profile to : santhosh.ajayakumar@insemitech.com

Company : InSemi Technology Location : Bengaluru Share Your Resume : santhosh.ajayakumar@insemitech.com

verification engineer

Looking for Mtech VLSI(passout-any year) candidate , who are trained in sv and uvm,

Company : Esilicon techno design privite limited Location : Bangalore Share Your Resume : hr@estdblr.com

Semiconductor Recruiter

- Recruit, interview, evaluate, and place highly skilled technical professionals on a product based client place in Europe across a wide array of Semiconductor positions. - Recruiting experience in Semiconductor / Hardware domain required or similar kind of knowledge is required.

Company : Indium Global Services Pvt. Ltd. Location : Whitefield (EPIP zone), Bangalore Share Your Resume : neha.kukde@indiumglobal.com

altran hiring VLSI freshers

VHDL based verification or knows VHDL....even M.Tech freshers, who may have learnt it during their curriculum pls share your profile with me suresh.pitchaimuthu@altran.com

Company : altran Location : Bengaluru Share Your Resume : suresh.pitchaimuthu@altran.com

Digicomm hiring VLSI Freshers walk in Drive

Digicomm hiring Freshers We are having a walk-in drive for M.E/M.Tech_Freshers for Frontend_Verification. Qualification- M.E/M.Tech (2016 and 2017, 2018 passed out) Interested candidates please come between 13th June to 15th June @10:00 AM to 3 PM Contact person- Ashwani Venu Details. # 4th Floor, Vaswani Presidio, Panathur Main Road, Off Outer Ring Road, Kaverappa Layout, Kaadubeesanahalli, Bangalore – 560103

Company : Digicomm Location : Bengaluru Share Your Resume : na

Hiring VLSI fresher at Synopsys

Looking for M Tech in VLSI 2017 / 2018 pass out for Intern / FTE position for Synopsys Hyderabad. If interested then email your profile to sarni@synopsys.com

Company : synopsys Location : Bengaluru Share Your Resume : sarni@synopsys.com

Hiring vlsi Freshers at black pepper

Hiring Freshers!!! Job Location: Bangalore Remuneration: 3 - 5 LPA First round : Written test (Descriptive only) Test Duration: 2 hours Topics to prepare: Computer Architecture, Logic Design, Digital Design, C/C++ coding, Analytical skills... Registration Links: Bangalore - https://lnkd.in/fMXxVAu Hyderabad - https://lnkd.in/f7-pYgG Bhubaneshwar - https://lnkd.in/fUJx9Vr Mangalore - https://lnkd.in/fXTDPRs Cochin -https://lnkd.in/f7xvdyc

Company : Black pepper Location : Bengaluru Share Your Resume : na

hiring Freshers ASIC Verification Engineer at VerifWorks

hiring Freshers ASIC Verification Engineer at VerifWorks apply 2015 & 2016 passout jobs@VerifWorks.com

Company : VerifWorks Location : Bengaluru Share Your Resume : jobs@VerifWorks.com

ASIC Verification Engineer

Experience: 2-15 years Location: Bangalore& Noida. Job Description: • Expert in UVM/OVM for Verification • System verilog assertions • Perl • Functional + Code Coverage • Verilog and VHDL • Tools like Synopsys VCS,Cadence IUS or Mentor Questasim is Preferable • Image Sensor knowledge is a plus • Experience with SPI,AHB,AXI,PCIe,DDR is a plus

Company : Radiant Semiconductors Pvt.Ltd Location : AECS Layout,Kundalahalli,Bangalore Share Your Resume : jobs@radiantsemi.com

HR person

We are looking for HR intership program , candidate with MBA -HR freshers can apply

Company : E silicon TechnoDesign private limited Location : Bangalore Share Your Resume : ashok.patil@estdblr.com

VERIFICATION ENGINEER

looking MTech intern for Design & verification - Mtech freshers

Company : E silicon TechnoDesign private limited Location : Bangalore Share Your Resume : ashok.patil@estdblr.com

VERIFICATION ENGINEER

ASIC design & Verification Engineers - MTech in VLSI and candidate must know SV & UVM Btech 2016 passout also can apply with above skill set

Company : E silicon TechnoDesign private limited Location : Bangalore Share Your Resume : ashok.patil@estdblr.com

VERIFICATION ENGINEER

we are looking for asic verification engineer who is having systemverilog and UVM knowledge

Company : E silicon TechnoDesign private limited Location : Bangalore Share Your Resume : ashok.patil@estdblr.com

VLSI freshers walkin drive at Eximius

VLSI fresher jobs-in for BE/BTec ECE, EEE freshers with 70% &andabove on 2nd June 18. Interested candidates directly walk in to below mentioned venue between 10:00 AM to 3 PM. Venue: Eximius Design Indiqube Alpha(Name of the building) 5th Floor Survey No: 19/4,227, Kadubeesanahalli Village Hobli Road, Bangalore - 560087 Land Mark - Diagonally opp to JP Morgan Bus Stop Name: JP Morgan or Kadubeesanhalli stop. POC: Veena/Roli

Company : eximius Location : Bangalore Share Your Resume : na

VLSI freshers walkin drive at ALTRAN

We are conducting freshers drive for physical Design on Saturday, 2. June 2018 at Whitefield Office Criteria. - Candidates must be trained in PD Domain - B.E / B.Tech / M.E / M.Tech - 2015 / 2016 / 2017 Graduates - Should have secured 70% + throughout academics. - PD Internship candidates are also eligible. Venue for Drive: Gopalan Global Axis, Tower A, 8th floor Road 9, KIADB Export Promotion Area, Whitefield, Bengaluru, Karnataka 560066 altran

Company : altran Location : Bangalore Share Your Resume : altran

Hiring VLSI Freshers at eximius

Hiring VLSI Freshers at eximius for ASIC design and verification Freshers Hiring for B.Tech(ECE, EEE) with 70% & above 2016/2017/2018 batch Interested candidates Kindly register in below link and only shortlisted candidates will be called for interview: https://lnkd.in/fNiUYFh Freshers Hiring for B.Tech(ECE, EEE) with 70% & above 2016/2017/2018 batch Interested candidates Kindly register in below link and only shortlisted candidates will be called for interview: https://lnkd.in/fNiUY

Company : eximius Location : Bangalore Share Your Resume : https://lnkd.in/fNiUYFh

Hiring VLSI Fresher at Tessolve

Greetings from Tessolve Semiconductor!!! We are hiring fresher’s passed out in 2017 who are trained in VLSI for the below domains. Candidates interested can drop their resumes to kavitha.mallikarjunaiah@tessolve.com • Analog Circuit Design • Analog/Custom Layout • AMS Verificatio

Company : Tessolve Location : Bangalore Share Your Resume : kavitha.mallikarjunaiah@tessolve.com

Infosys is hiring Freshers for Systems Engineer

Infosys is hiring Freshers Role: Systems Engineer Eligibility Criteria: • BE / B.Tech / ME / M.Tech in any discipline • MCA / MSc (Computer Science / Electronics / Mathematics / Physics / Statistics / IT / Information Science) • Consistently excellent academic track record • Candidates graduating in 2018 Details Required: 1. Full Name: 2. Primary Email: 3. Mobile no.: 4. D.O.B: 5. 10th % or CGPA: 6. 12th % or CGPA: 7. Diploma(If Applicable): 8. Graduation details: • college, state • cgpa • stream 9. Post Graduation details: • college, state • cgpa • stream 10. Preferred Test Location: Last date for receiving referrals: June 4, 2018 Interested Candidates mail above details with subject Referral for 2018 Pass out tushar.varshney@infosys.com

Company : Infosys Location : Bangalore Share Your Resume : tushar.varshney@infosys.com

Hiring VLSI Freshers at pathpartnertech

Hiring B.Tech/M.Tech Freshers(Electronics background) Passed out in the year 2018 for Bangalore Location. We have multiple openings here. Interested folks can share their resume at nagma.sultana@pathpartnertech.com

Company : pathpartnertech Location : chennai Share Your Resume : nagma.sultana@pathpartnertech.com

Mask Design or Custom Layout

Custom Layout implementation of Analog blocks/Top, feasibility analysis, floor plan, power plan, good understanding of delay aspects and ECO flow, and familiar with challenges at deep micron effects. Minimum 3-15 years industry experience Worked on multiple blocks/top Good understanding of ECO flow

Company : Thinsil Technologies Location : Penang-Malaysia, Bangalore-India Share Your Resume : lahari@thinsil.com

FPGA Validation Enginners

4-15 Years Experience Experience with FPGA Systems Expertise in System Verilog Test content development (Maestro,Firmware based) Test Execution

Company : Thinsil Technologies Location : Penang-Malaysia Share Your Resume : lahari@thinsil.com

Physical Design Engineer

Please go through the JD for better understanding: • Perform Floor-planning and Placement, CTS, Routing. • Knowledge of full RTL to GDSII flow (, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop ) • Hands-on experience with synopsys and Cadence PnR tools, Floorplaning, IR Drop and Physical verification - Should have good understanding of verilog/VHDL • Exposure to low power techniques • Knowledge of tcl and perl scripting is desirable • Team player, flexible, good communicator Qualification • Minimum Qualifications Educational qualification: B Tech / M.Tech This position is full-time and we offer a competitive salary. If you have a forward-thinking attitude and are ready to go the extra mile with us, we look forward to receiving your application.

Company : Si2chip Pvt Ltd. Location : Bangalore Share Your Resume : himanshu.pandey@si2chip.com

VLSI Walk in drive for Junior ASICVerification Engineers at radiantsemi

Weekend Walk-in drive for Junior ASICVerification Engineers Exp 0.6 to 1.5 years written test and interview on MAY 26th 2018 shortlisted candidates are eligible for interviews Note : Shortlisted Candidates are eligible for Interviews Last date to Apply : 23-May-2018 Email : fresher@radiantsemi.com

Company : radiantsemi Location : Bangalore Share Your Resume : fresher@radiantsemi.com

Openings for Verification Freshers at Digicomm

Openings for Verification Freshers...!!!!!!!!! Immediate Openings for ASIC Verification Engineers @ DC Semiconductor...!!! We are currently hiring Verification engineers having the training or internship experience with M.tech(VLSI) Location:- Bangaluru Experience:- Freshers Interested candidate can call(916263270625) or share your resume with supriya@digicomm.org

Company : digicomm Location : Bangalore Share Your Resume : supriya@digicomm.org

VLSI Internship at Synopsys

One year Internship at Synopsys, Mumbai for development profile. Looking for B.Tech/M.tech 2017/ 2018 pass out with Perl, TCL skills. JD: Will be required to carry out the Software development as per the SDLC. Basic programming/scripting knowledge Should have good communication skills An aptitude to learn Interested candidates mail ur profile to akpv@synopsys.com

Company : synopsys Location : Mumbai Share Your Resume : akpv@synopsys.com

Fresher ASIC Verification and ASIC Physical Design Engg at to numascale

Currently we have openings in ASIC Verification and ASIC Physical Design Engg. for freshers and experienced engineers. We are conducting an exclusive recruitment drive in the end of June, if you are interested please send your updated resume to vb@numascale.com. Only short-listed candidates would appear in recruitment drive.

Company : numascale Location : Ahmedabad Share Your Resume : vb@numascale.com

VLSi freshers jobsat Black Pepper Technologies

Interview call letter with Black Pepper Technologies BLACK PEPPER The Spice of Innovations Qualification : MTech or ME Electrical & Communication 2018, 2017 with minimum 65 aggregate Date : 18th May 2018 Friday

Company : Black Pepper Technologies Location : Bangalore Share Your Resume : https://lnkd.in/frKR5BC

Dexcel is hiring for Trainee Validation Engineers

Dexcel is hiring for Trainee Validation Engineers. Criteria: B.E/ B.Tech in Electronics Fresh Graduates who have undergone training in Embedded Systems/ Testing Send profiles to careers@dexceldesigns.com Availability: Immediate

Company : dexceldesigns Location : Bangalore Share Your Resume : careers@dexceldesigns.com

Hiring VLSI Fresher at ust global

Hiring VLSI 2017 Freshers for Noida with 75 % Marks in BE/ Mtech for Noida Please share if your profile at u53040@ust-global.com

Company : ust global Location : Noida Share Your Resume : u53040@ust-global.com

hiring DFT fresher at skandysys

Looking for M.Tech Freshers/ Trained Engineers in DFT for Bangalore location. Candidates must have minimum of 70% aggregate. Applications with 2016/207/2018 will be considered. please share your resumes at lavanyaks@skandysys.com. Candidates who have appeared for in the recent past need not apply.

Company : skandysys Location : Bangalore Share Your Resume : lavanyaks@skandysys.com

hiring VLSI freshers at blackpeppertech

Opportunities for M.tech Freshers. Skill Requirements: Physical Design, Design Verification, RTL Design and DFT Qualifications: M.Tech with minimum 70% aggregate Send me your profile to: goutam.padhy@blackpeppertech.com with your updated resume

Company : blackpeppertech Location : Bangalore Share Your Resume : goutam.padhy@blackpeppertech.com

Relicuus Hiring MTech VLSI Design Interns

Excellent Knowledge in Digital Logic and Verilog .Excellent debugging and problem solving skills. Excellent written and verbal communication skills Only Preferred M.Tech with Gate Qualified Candidates. Interview Process: 1.online test 2.F2F technical discussion (2 rounds) Please use below link to attend online test any time. http://www.relicuussemi.com/online_test

Company : RELICUUS SEMICONDUCTOR PRIVATE LIMITED Location : Bangalore Share Your Resume : hr@relicuussemi.com

Verification

hiring M.tech Freshers who having training or internship in ASIC verification

Company : Digicomm Location : Bangalore Share Your Resume : Supriya@digicomm.org

Hiring Freshers in ASIC Verification

Looking M.Tech Freshers/ Trained Engineers in Verification for Bangalore location. Must have minimum aggregate of 70%

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

Hiring Freshers in ASIC Verification

Looking M.Tech Freshers/ Trained Engineers in Verification for Bangalore location. Must have minimum aggregate of 70%

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

Memory Layout Engineer

Requirements • Experience: 3 - 6 Years. • Work Location : Taiwan Skills required: • Experience in memory mask design, SRAM, FINFET. • Should have experience working in technologies 45nm and below. • Should have experience in drawing memory core arrays, write drivers and control circuits. • Should have sound knowledge of DFM concepts; knowledge of double patterning and colouring concepts are a plus. • Knowledge of SKILL scripting language is preferred. Job Description: • Mask design work on various building blocks of memory or Register file design. Eg. Drawing mux cells, decoders, memory control, sense amplifiers etc. • Drawing memory core arrays with proper termination at edges, corners and straps. • The top level integration of memory instances in memory compiler Environment. • Regression DRC, LVS, density clean-up of memory instances across Memory compiler space. • The IR/EM testing and fixes of memory instances.

Company : Savvychip Technologies Location : Taiwan Share Your Resume : careers@savvychip.com

Memory Layout Engineer

Requirements • Experience: 3 - 6 Years. • Work Location : Taiwan Skills required: • Experience in memory mask design, SRAM, FINFET. • Should have experience working in technologies 45nm and below. • Should have experience in drawing memory core arrays, write drivers and control circuits. • Should have sound knowledge of DFM concepts; knowledge of double patterning and colouring concepts are a plus. • Knowledge of SKILL scripting language is preferred. Job Description: • Mask design work on various building blocks of memory or Register file design. Eg. Drawing mux cells, decoders, memory control, sense amplifiers etc. • Drawing memory core arrays with proper termination at edges, corners and straps. • The top level integration of memory instances in memory compiler Environment. • Regression DRC, LVS, density clean-up of memory instances across Memory compiler space. • The IR/EM testing and fixes of memory instances.

Company : Savvychip Technologies Location : Taiwan Share Your Resume : careers@savvychip.com

Memory Layout Engineer

Requirements • Experience: 3 - 6 Years. • Work Location : Taiwan Skills required: • Experience in memory mask design, SRAM, FINFET. • Should have experience working in technologies 45nm and below. • Should have experience in drawing memory core arrays, write drivers and control circuits. • Should have sound knowledge of DFM concepts; knowledge of double patterning and colouring concepts are a plus. • Knowledge of SKILL scripting language is preferred. Job Description: • Mask design work on various building blocks of memory or Register file design. Eg. Drawing mux cells, decoders, memory control, sense amplifiers etc. • Drawing memory core arrays with proper termination at edges, corners and straps. • The top level integration of memory instances in memory compiler Environment. • Regression DRC, LVS, density clean-up of memory instances across Memory compiler space. • The IR/EM testing and fixes of memory instances.

Company : Savvychip Technologies Location : Taiwan Share Your Resume : careers@savvychip.com

Memory Layout Engineer

Requirements • Experience: 3 - 6 Years. • Work Location : Taiwan Skills required: • Experience in memory mask design, SRAM, FINFET. • Should have experience working in technologies 45nm and below. • Should have experience in drawing memory core arrays, write drivers and control circuits. • Should have sound knowledge of DFM concepts; knowledge of double patterning and colouring concepts are a plus. • Knowledge of SKILL scripting language is preferred. Job Description: • Mask design work on various building blocks of memory or Register file design. Eg. Drawing mux cells, decoders, memory control, sense amplifiers etc. • Drawing memory core arrays with proper termination at edges, corners and straps. • The top level integration of memory instances in memory compiler Environment. • Regression DRC, LVS, density clean-up of memory instances across Memory compiler space. • The IR/EM testing and fixes of memory instances.

Company : Savvychip Technologies Location : Taiwan Share Your Resume : careers@savvychip.com

hiring VLSI fresher at firstpass semi

" Hiring 2016 and 2017 freshers for Design & Verification position. Looking for candidates who have 70% and above percentage and also trained/done internship in System Verilog, UVM. Interviews will be conducted in May-2018. Interested candidates can drop me your resumes to madhav.motakadi@firstpass-semi.com

Company : firstpass semi Location : hydarabad Share Your Resume : madhav.motakadi@firstpass-semi.com

hiring for Freshers zilogic

Freshers with M.tech in Communication Engineering have done their projects on RF / Wireless technologies can apply for a challenging opportunity in Chennai. Candidates with good knowledge in Wireless Networking, MAC, PHY in addition to above basic skill set can easily crack the interview. Interested, pls share your profile to anandharaj@zilogic.com

Company : zilogic Location : chennai Share Your Resume : anandharaj@zilogic.com

EXIMIUS is hiring Fresher for ASIC Design Verification

EXIMIUS is hiring M.Tech Graduates in Design Verification Education M. Tech in ECE / EE Please use below link for registrations https://goo.gl/forms/wXE5HANPrTkz1RPU2 Shortlisted candidates will be called for the interview Registrations will close on 10th May

Company : EXIMIUS Location : Bangalore Share Your Resume : https://goo.gl/forms/wXE5HANPrTkz1RPU2

hiring vlsi freshers at Test and verification

DFT /DFX VLSI Engineers We are hiring enginceting professionals with meniioned discipline who believes in cmyonc is unique, with unique values and ideas. Cligibilitg Good educational background (above 800/0), VLSI as specialization with Embedded and VLSI courses. Selection Process Written Test , Presentation on "Structural & Adhoc Testing in VLSI" for 5 mins Technical discussion Dotes to remember 5th May 2018 : Deadline for appling 12th May 2018 Selection doss fie6 mat.er yOu p as lotis as pu do hot st," -Confucius ramanathan.ct@testandverification.com pradeepkumart@testandverification.com

Company : TEST AND VERIFICATION SOLUTION Location : Bangalore Share Your Resume : pradeepkumart@testandverification.com

VLSI Interns at Relicuus

Good Knowledge in Digital Logic and Verilog . Knowledge of C/C++ would be an added advantage. excellent debugging and problem solving skills. Excellent written and verbal communication skills Only Preferred Gate Qualified Candidates

Company : RELICUUS SEMICONDUCTOR PRIVATE LIMITED Location : Bangalore Share Your Resume : hr@relicuussemi.com

IP And SoC VerificationEngineers

Responsible to develop test plan, test cases and verification components.

Company : Vaaluka Solutions Location : Hyderabad Share Your Resume : careers@vaalukasolutions.com

STA

Experience: 1 to 15yrs, Understanding of SoC architecture, clocking, reset, data flow, multi-voltage needs SoC & Partition-level constraints development (clocks, exceptions), SoC IO interface/ACIO constraints, DFT (shift, stuckat, atspeed, mbist) constraints Partition IO time budgeting & constraints push-down from SoC top (understanding of PT-context/hyperscale is a plus) Clock tree analysis skills (balancing need, latency & skew analysis, debugging of issues) Timing Analysis/triazing/debugging skill, Timing ECOs/fixes (DMSA/Tweaker) in multi-mode/multi-corner & what-if analysis ß Timing margin & PVT/RC corner understanding Timing regression runs in all modes/corners & signoff

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

RTL Design

Experience: 2 to 15yrs, "Experience in Logic design / Micro-architecture / RTL coding is a must. Expertise in Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB. Experience in Synthesis / Understanding of timing concepts for ASIC is required."

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

Opportunity in DFT

Experience: 1 to 15yrs, Strong knowledge of DFT techniques JTAG, MBIST, P1500, Core-Based Testing Standards, scan, on-chip scan compression, fault models, ATPG, fault simulation and AC scan for at speed testing Good experience with any commercial ATPG & Simulation EDA Tools Good experience with any commercial MBIST & JTAG solution. Experience in simulation on zero delay and SDF Excellent debug skill ß Ability to communicate effectively with multiple global cross-functional teams"

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

Physical Design Opportunity with BlackPepper Technologies

Experience: 1 to 15yrs, "We are looking for people with below experiences, Technologies from 28nm, 20nm, 14nm, 10nm,7nm. Block level floorplanning, power planning and IR drop analysis. Timing closure Multimode multi corner optimization and closure. Clock tree synthesis and advanced clock tree implementation. ß Block level timing closure with sign off STA . Block level ECO implementation involving netlist level logical changes. Library performance analysis and fine tuning for implementation. Excellent debugging skills in implementation issues and ability to come up with creative solutions . Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C, C++. EDA Tools:IC compiler,Cadence Encounter,Prime Time, Tweaker,Conformal LEC, Calibre, Star-RC, Laker."

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

ASIC Verification

"Have working knowledge of UVM/SYSTEM VERILOG, Have worked on IP and/or SoC Verification, Have working knowledge of Standard bus protocol such AXI/AHB/APB etc. Have working knowledge of interface protocol UART,USB,I2C etc" Experience: 3 to 12yrs

Company : BlackPepper Technologies Location : Bangalore Share Your Resume : mala.srinivas@blackpeppertech.com

Asic Verification

Experience: 3 to 15 years Job Location: Bangalore / Hyderabad / Pune Notice period: 30 days Job Role • Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level • Develop IP level/SoC level test plans based on the design/architectural specs. • Coverage Analysis and Coding • Run simulations & regressions, debug test failures to identify test case issues & RTL design issues • Define and develop block/full chip level verification environment and its components Required Skill • Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies • Good understanding of RTL concepts • Good understanding of AHB/AXI protocol • Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage • Knowledge of Perl/TCL is Must • Good communication skill

Company : Smartbytes Technology Location : Bangalore Share Your Resume : girishp@smartbytestech.com

DFT Engineer

Exp : 3- 13 yrs Job Location : Bangalore / Hyderabad / Pune Work involves DFT Architecture definition for a cutting-edge, high-speed SoC. Along with DFT architecture definition the team would be responsible for test plan definition, hierarchical block DFT, RTL integration, MBIST using SMS, ATPG for blocks and full chip, pattern simulations, and DFT timing closure. Good understanding of DFT concepts and flows, test structures and test techniques DFT implementation using DC/RC, Tessent/Tmax, SMS/Mentor memory BIST, Mentor B-scan Expertise in ATPG tools and coverage analysis, ATPG Pattern Simulation & Retarget (Zero Delay & SDF) Implementation of DFT specification for blocks, independently handle IP verification Good exposure to Synthesis & STA tool. Assist STA team in timing closure for DFT modes Good scripting skills (TCL/Perl)

Company : Smartbytes Technology Location : Bangalore Share Your Resume : girishp@smartbytestech.com

VLSI Verification Engineer opportunity at sivetech

VLSI Verification Engineer opportunity. Interview Drive on Saturday, April 28,2018 for Mtech freshers at NOIDA Intersted people share your updated resume at hr@sivetech.com with the subject line 28/04 interview. SiveTech is hiring!(NOIDA location only) We are looking for passionate VLSI Design Engineer. Job Type: Full-time Salary: ₹400,000.00 to ₹600,000.00 /year Preferred: Mtech in VLSI Design with frontend project knowledge. Skills required: Verilog/VHDL, C/C++, System Verilog Salary offered: 4-6 LPA

Company : sivetech Location : Bangalore Share Your Resume : hr@sivetech.com

Hiring for VLSI freshers

Hiring for M.Tech freshers. Must be into VLSI domain. Only 2017 or 2018 passed outs or considered. Must be available for F2F discussion once your profile get shortlisted. Interested candidates please share resumes to t.saisruthi@mobiveil.co.in.

Company : mobiveil Location : Bangalore Share Your Resume : t.saisruthi@mobiveil.co.in

eInfochips hiring for Design Verification engineer

eInfochips, an Arrow company is hiring for Design Verification engineer for Pune office. Ideal candidate should have hands on experience on System Verilog, Methodology like UVM/OVM/ VMM, AMBA, AXI, AHB. Interested one sent me your profile to furkan.khan@einfochips.com

Company : eInfochips Location : Pune Share Your Resume : furkan.khan@einfochips.com

Tejas Networks is hiring for a BE BTech fresher

Tejas Networks is hiring for a B.E/B.Tech fresher [2016/2017] - R&D product team. Please write to swethar@india.tejasnetworks.com Note: Good English written and verbal communication is must.

Company : tejasnetworks Location : Bangalore Share Your Resume : swethar@india.tejasnetworks.com

Digicomm is hiring Verification Trained Fresher

Digicomm is hiring #Verification_Trained_Fresher ! Qualification:- #Only_Master_degree ME/M.Tech (Pass out year 2014,2015,2016) Please mail your resume at ashwani.kumar@digicomm.org

Company : DIGICOMM Semiconductor Private Limited Location : bangalore Share Your Resume : ashwani.kumar@digicomm.org

INTERN at Maxim Integrated

Design of AC-DC and DC-DC High Frequency Switching Power Supplies with Maxim’s large selection of Power Management Integrated Circuits to provide compelling customer solutions. New AC-DC and DC-DC controller definition and validation.

Company : Maxim Integrated Location : Bangalore Share Your Resume : https://sjobs.brassring.com/tgwebhost/jobdetails.aspx?jobId=471321&PartnerId=26065&SiteId=55

VLSI freshers at open silicon

Hiring VLSI freshers at open silicon Hiring VLSI freshers at open silicon 2018 batch pass outs of MTech specialized in ECE/EEE/VLSI/Electronics Company : open siliconLocation :BangaloreShare Your Resume : careers.india@open-silicon.com

Company : open silicon Location : Bangalore Share Your Resume : careers.india@open-silicon.com

Embedded Product development

Walk IN :Job Assured Embedded Product development in Vehicle Electronics Program Qualification : B.E / M Tech ( EEE, ECE, Mechatronics, E&C with 60% , 2016 & 2017 passed out candidates) SEINE is developing a rescue automotive vehicle with an integrated UAV for aerial surveillance and various civilian rescue applications. The Vetronics scope involves development need of Advanced Driver Assist/ driver Infotainment & Connectivity / Body& Comfort System etc. To meet our internal and client needs, currently We are running a Job assured 8 weeks Vehicle Electronics Embedded Product Development program for selected candidates, on completion of Internship, They will be absorbed as Project Engineer in the Vehicle Electronics Engineering Team. Number of Position : 10 - Contact : +9195137 42993 or email dqms@seine-aerospace.com for appointment - Walk in Location : Seine Product Design P Ltd - 2nd Floor ,CM Plaza, Jakkasandra, Koramangala First Block, Bangalore, India. 560 034

Company : seine aerospace Location : Bangalore Share Your Resume : dqms@seine-aerospace.com

Physical design Engineer

floor planning,routing,PNR, ICC must.

Company : Whizchip design technologies Location : Bangalore Share Your Resume : rekhap@whizchip.com

Physical Design or Verification Engineers

We got a requirement on Physical Design/Verification Engineer, If you or any of your friends are looking for job Change, share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 3 - 12 Years of Experience. • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. Job Description: • Hands on Experience in PD Design / Verification. • Hands on experience in running STA & Synthesis. • Hands on experience in design Timing closure, Clock/Power distribution/analysis, RC Extraction, P & R, Floorplan, Place & Route, CTS, SI Avoidance/fixing, power, clock, noise, IR/EM analysis, LEC for block level. • Hands on experience in verification DRC, LVS, DFM, Density checks, report generation, debugging. • Hands on experience in scripting language Tcl/Perl/Python. • Responsible for PD Implementation of complex ASIC/SoCs. Interested Professionals with minimum of 3 years of experience can send their Updated profiles to careers@savvychip.com. Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : Physical Design/ Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore / Malaysia/ Singapore Share Your Resume : careers@savvychip.com

ASIC Verification Engineers

We got a requirement on ASIC Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 3 - 12 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Chennai. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 3 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : ASIC Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore/ Hyderabad / Chennai Share Your Resume : careers@savvychip.com

ASIC Verification Engineers

We got a requirement on ASIC Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 3 - 12 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Chennai. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 3 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : ASIC Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore/ Hyderabad / Chennai Share Your Resume : careers@savvychip.com

ASIC Verification Engineers

We got a requirement on ASIC Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 3 - 12 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Chennai. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 3 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : ASIC Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore/ Hyderabad / Chennai Share Your Resume : careers@savvychip.com

ASIC Verification Engineers

We got a requirement on ASIC Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 3 - 12 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Chennai. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 3 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : ASIC Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore/ Hyderabad / Chennai Share Your Resume : careers@savvychip.com

Excellent opportunities for VLSI Interns orTrainee Engineers

Frenus Tech Pvt Ltd, Bangalore. Excellent opportunities for VLSI Interns/Trainee Engineers. Positions: 1. ASIC/SoC Design and Verification Engineer. 2. Physical Design Engineer. Mandatory to have: Educational Qualification: BE/B.Tech or ME/M.Tech. Experience: 1+ Years as interns/trainee into above technologies. Interested candidates. Pls share CV via Deven.kr@frenustech.com

Company : frenustech Location : Bangalore Share Your Resume : Deven.kr@frenustech.com

hiring for physical Design Trained Freshers

looking for PD Trained Freshers with 2017 / 2018 Pass out only. Kindly share the updated profile @ veena.patil@si2chip.com

Company : si2chip Location : Bangalore Share Your Resume : veena.patil@si2chip.com

Electronic fresher jobs

openings for "Quote Representative" Eligible criteria Qualification: B.sc Electronics, B.E in Electronics Experience: 0-2 years Location: Bangalore Open positions:2 Job description: Pricing, Quotation etc.. (detailed JD will be shared over email). Please send your CV to: sreepriyanka.r@mouser.com or call on 080-42650000 extn: 4256.

Company : mouser Location : bangalore Share Your Resume : sreepriyanka.r@mouser.com

Cerium is hiring Freshers

Cerium is hiring Freshers - 2017 passed outs only Education: B.tech/B.E/M.Tech in E.C.E / E.E.E Drop your CV to freshers@cerium-systems.com Can apply till 12th April only

Company : cerium systems Location : Bangalore Share Your Resume : freshers@cerium-systems.com

Analog Circuit Design Engineer

Looking for Circuit Design Engineer for Bangalore Location.. Experience- 6 months - 2 years Please Share CVs to ridam.jaiswal@open-silicon.com

Company : open silicon Location : Bangalore Share Your Resume : ridam.jaiswal@open-silicon.com

DFT ATPG Engineer

Expertise in ATPG tools and coverage analysis, ATPG Pattern Simulation & Retarget (Zero Delay & SDF) Experience : 2 to 7 Years

Company : Vaaluka Solutions Location : Hyderabad Share Your Resume : careers@vaalukasolutions.com

RTL Design Engineer

Looking for RTL Design engineers with IP and SoC experience. Experience range: 4 to 10 Years

Company : Vaaluka SOlutions Location : Hyderabad Share Your Resume : careers@vaalukasolutions.com

DFT Engineer

Looking for DFT Engineers with Experience range 2 to 10 years. Location: Hyderabad, Bangalore, Pune

Company : Vaaluka SOlutions Location : Hyderabad Share Your Resume : careers@vaalukasolutions.com

AISC Verification

IP, SoC Verification.

Company : Vaaluka SOlutions Location : Hyderabad Share Your Resume : careers@vaalukasolutions.com

Physical Design Engineer

A good understanding of electrical, timing and reliability issues in deep sub-micron circuit design is require. Ability to plan and work independently and co-ordinate with cross-functional teams across geographies is essential. The job would require scripting in Synopsys Tcl and an expertise in physical verification. Good understanding of industry EDA tools used in Physical Design, including but not limited to Design Compiler, DFT Compiler, ICC2, StarXT, PrimeTime and Calibre.

Company : Maxvy technologies Pvt Ltd Location : Bangalore Share Your Resume : http://asicjobz.com/job-detail.html?id=AJZ536839

STA Engineer

Job Description Qualification : B.E / B.Tech/M.Tech Description : - Experience in synthesis of complex SoCs block/top level and writing timing constraints - Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints - Experience in post-layout STA closure and timing ECOs - Worked in technology nodes 45nm and below - Knowledge of low-power aware implementation is a plus Tools : RTL Compiler, LEC, CLP, ETS/PTSI/GT

Company : SmartSoc Solutions Location : Hyderabad/Bengaluru Share Your Resume : recruit@smartsocs.com

Hiring VLSI freshers for Design and Verification position at firstpass semi

Hiring 2016 and 2017 freshers for Design & Verification position. Looking for candidates who have 70% and above percentage and also trained/done internship in System Verilog, UVM. Interviews will be conducted in April-2018. Interested candidates can drop me your resumes to madhav.motakadi@firstpass-semi.com

Company : firstpass semi Location : hydarabad Share Your Resume : madhav.motakadi@firstpass-semi.com

Physical Design trained candidates

Dear All, We are hiring Physical Design trained candidates for our upcoming requirements. We are looking for candidates who have undergone training in VLSI post completion of engineering from any of the training institutes. Please find below the eligibility criteria: B. Tech/B.E/ M. Tech with the percentage of 60 and above. Job Location: India Training/course completion certificate is mandatory to appear for the interview process. If you have some references please forward us the resumes @raka.mondal@aricent.com Happy hiring !! Thanks & Regards, Raka Mondal ARICENT, Bangalore

Company : Aricent Location : Bangalore Share Your Resume : raka.mondal@aricent.com

hiring ASIC Verification Engineers

Esilicon Technodesign Private Limited We are hiring ASIC Verification Engineers 1.MTech freshers trained for 6 months with good knowledge in SV &UVM 2.ASIC Verification Engineers with 1-3 year experience. 3.Physical Design Engineers with 1-3 year of experience ,for Bangalore location . Interested candidates can mail their CV to hr@estdblr.com

Company : estdblr Location : Bangalore Share Your Resume : hr@estdblr.com

Openings For Freshers Trained for Analog Layout Analog Circuit Design

Openings For Freshers & Trained for Analog Layout & Analog Circuit Design. Interested Candidate can share CV to madhvit@eximiusdesign.com

Company : eximiusdesign Location : Bangalore Share Your Resume : madhvit@eximiusdesign.com

hiring for VLSI Fresher intern position at dexceldesigns

Greeting Dexcel designs!!! We are hiring for VLSI Fresher intern position.. Experience: fresher Location: Bangalore Education: M.Tech (VLSI)Background Applicants Only Preferable.. If Interested applicants reach me on kumar.vajjiravelu@dexceldesigns.com

Company : dexceldesigns Location : Bangalore Share Your Resume : kumar.vajjiravelu@dexceldesigns.com

hiring VLSI Interns at insilicorp

Insilico hiring Intern(B.E: EE/EEE/EC/CS) for Bangalore, interested candidate send me your resume on Mayanks@insilicorp.com

Company : insilicorp Location : Bangalore Share Your Resume : Mayanks@insilicorp.com

RTL Design Engineer

MS / M-Tech in VLSI or similar stream with minimum 7-18 yrs of relevant experience in RTL design/SoC Integration Expertise in some or al protocols: SD host 3.0, Ethernet, ONFI 3.1 NAND, video encoder/decoder Work experience in ARM andl AXI bus based system, knowledge of memory controller required Knowledge in Low power design methodology is plus Proficient in static timing analysis (primetime based). Have at least closed Prime time based timing closure for at least one SoC Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis, should be able to create synthesis constraints based on design requirements Have good knowledge in scripting language like perl/python (optional) Should have knowledge in clock-domain crossing(CDC, Spyglass, 0in), Linting(Spyglass) and other RTL quality checks Team player with ability to work w/ multisite and local teams.

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

Digital Design Engineer

Responsibilities: § Develop key blocks of logic in a next generation physical layer/mixed signal SOCs § Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design § Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation Requirements: § Minimum BE/BS degree in Electrical/Electronics/Computer science required § At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts § Experience in physical layer ASIC architecture, micro-architecture development, design and debug § Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog § Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows and scripting § Knowledge in one or more of the following areas, a definite plus • Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer) • DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding • Computer architecture/Processor fundamentals Preferred Qualifications: § Strong knowledge of ASIC design methodologies and flows § Ability to proactively take on responsibilities and competent to work in a start-up environment § Worked with product development companies and having seen at least a couple of tape-outs § Experience with silicon bring-up in the lab and debugging is a definite plus § Experience with FPGA realizations of higher complexity designs § Ability to work with teams spread across geography with excellent communication skills

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

Principal ASIC Design Engineer for MAC

- 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience with Networking protocol and implementations - RTL Design and implementation of Switch/MAC/PTP/PCS cores and offload engines for high performance networking applications - Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals - Review vendor IP integration guidelines and verify the compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines - Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality - Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals - Be able to work and communicate with multi-site teams - Responsible for the review of netlist releases (pre/post-route/eco, block/chip) - ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

Principal ASIC Design Engineer

- 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes) - Experience with CSI/DSI debug - RTL Design and implementation of CSI/DSI controllers - Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals - Review vendor IP integration guidelines and verify the compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines - Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality - Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals - Be able to work and communicate with multi-site teams - Responsible for the review of netlist releases (pre/post-route/eco, block/chip) - ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

Principal FPGA Design Engineer

- 10+ years of FPGA Design and Debug experience (preferably with Xilinx Ultrascale+ and Virtex7) - Proficiency in using Xilinx Vivado/Coregen/Synplify and development/maintenance of Timing/IO constraints (UCF) - Experience with multiple high speed clock domains - Experience with integration of third-party IP (PCIe controller, Serdes PCS) onto Xilinx transceivers - Experience working with FMC daughter-cards, High-Speed Cables/Connectors etc. - Extensive debug experience using Xilinx ILA and Protocol Analyzers, Oscilloscope, Logic Analyzers etc. - Proficiency in PERL/TCL scripting - Database management between FPGA and ASIC RTL - Familiarity with front-end RTL tools (RTL Simulation, Synthesis, DFT, Timing) - RTL Design modification/adaptation for FPGA implementation (memories, IO, clocking etc.) - Design optimization to achieve FPGA area/performance goals - Work closely with DV and Firmware/Software teams during the entire validation process; including post-silicon bring-up - Be able to work and communicate with multi-site teams - Responsible for the review of FPGA netlist releases (block/chip) - ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

Principal ASIC Design Engineer for Network Security

- 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience with MACSEC/IPSEC protocol and security implementations - RTL Design and implementation of MACSEC/IPSEC/AES/SHA/RSA cores for high performance networking application - Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals - Review vendor IP integration guidelines and verify the compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines - Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality - Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals - Be able to work and communicate with multi-site teams - Responsible for the review of netlist releases (pre/post-route/eco, block/chip) - ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

Principal ASIC Design Engineer PCI Design and Integration

Experience/Skills: - 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency - Experience with multiple clock and power domains - Extensive experience in integration and validation of high speed PCIe IP core (including controller and PHY SerDes) - Experience with PCIe protocol analyzers and debug - Familiarity with PCIe driver and application software for Linux/Windows - RTL Design and implementation of interface logic between PCIe controller and DMA engines for high performance networking application - Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals - Review vendor IP integration guidelines and verify the compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines - Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality - Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals - Be able to work and communicate with multi-site teams - Responsible for the review of netlist releases (pre/post-route/eco, block/chip) - ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

DIGITAL DESIGN VERIFICATION

Responsibilities: 8 to 15 years of DV experience in building and architecting verification environments, preferably from scratch for multiple projects. The engineer should have experience in writing test plan, creating & enhancing verification environments and be comfortable coding any portion of a test bench (models, checkers, scoreboards, coverage monitors, etc.). Candidate should have experience in the development of constraint random DV environments for large ASIC blocks. Qualifications: Languages: Must have experience in Verilog/SystemVerilog. Methodology: Strong UVM (must) and Specman (is a plus). Formal verification experience is a plus. Experience with C++ is a plus. Experience with Automotive, MIPI PHY standards. Experience with PCIe and/or networking (Ethernet/PCS) protocol. Experience with gate level simulation and debug. Scripting: Perl, Python. Experience with SoC verification. Good interpersonal/communication skill. Experience in assertion methodology, emulation/hardware acceleration platforms is a plus.

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

DIGITAL DESIGN VERIFICATION

Responsibilities: 8 to 15 years of DV experience in building and architecting verification environments, preferably from scratch for multiple projects. The engineer should have experience in writing test plan, creating & enhancing verification environments and be comfortable coding any portion of a test bench (models, checkers, scoreboards, coverage monitors, etc.). Candidate should have experience in the development of constraint random DV environments for large ASIC blocks. Qualifications: Languages: Must have experience in Verilog/SystemVerilog. Methodology: Strong UVM (must) and Specman (is a plus). Formal verification experience is a plus. Experience with C++ is a plus. Experience with Automotive, MIPI PHY standards. Experience with PCIe and/or networking (Ethernet/PCS) protocol. Experience with gate level simulation and debug. Scripting: Perl, Python. Experience with SoC verification. Good interpersonal/communication skill. Experience in assertion methodology, emulation/hardware acceleration platforms is a plus.

Company : Client of Koral- Product based MNC Location : Bangalore & Hyderabad Share Your Resume : koraljobs@koralconsultants.net

DFT Manager Engineer openings

Mid level DFT engineer ( Manager/ Sr. Manager role same skill set with people management skills) Job Requirements : • BE/ME or equivalent with 10- 20 years experience in DFT on complex SOC designs using industry standard DFT flows, preferably from Mentor Graphics • Hands-on experience on ASIC/SOC design, verification flows and methodologies • Knowledge of Boundary scan/JTAG/BSDL • Solid knowledge of Scan and BIST is essential • Understanding with Verilog/VHDL • Familiarity with Scan insertion/tracing • ATPG, stuck-at, at-speed coverage reporting/enhancement • Pattern/vector generation • Debugging skills with timing simulations • Formal verification and Lint tools experience desirable • Interface with RTL integration, PD and FV engineers to resolve/debug issues • Very good communication skills • Outstanding analytical and critical thinking skills. • Expertise in scripting language such as PERL, TCL is highly desirable.

Company : One of the top notch client of Creeno solutions Pvt Ltd Location : Hyderabad Share Your Resume : sai@creenosolutions.com

hiring for freshers DSP

Hiring M.Tech Freshers from IIT/NIT/VIT/Bits Pilani who passed in year 2016/17 with Primary field as DSP/Signal Processing /Image Processing/ Optimization for Bangalore Location. We have multiple openings here. Interested folks can share their resume at prudhvi.reddy@pathpartnertech.com

Company : pathpartnertech Location : Bangalore Share Your Resume : prudhvi.reddy@pathpartnertech.com

ASIC Verification Engineers

We got a requirement on ASIC Design or Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 2 - 10 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 2 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

ASIC Verification Engineers

We got a requirement on ASIC Design or Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 2 - 10 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 2 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

Hiring VLSI interns

Hiring VLSI interns JD Job Description: The position requires learning and applying modern verification tools on IC designs. Requirements: Strong educational background with a BTech in Computer Science or Electrical Engineering from an IIT, or an equivalent college. 0-2 years of work experience. Exceptional problem-solving skills. Desirable, but not required: Familiarity with the ASIC design and verification flow.

Company : na Location : Bangalore Share Your Resume : vlsiinternship@gmail.com

Cadence is Hiring for Freshers Intern position

B.E/B,Tech/M.Tech Computer Science (CS) pass-out with above 75% or 7.5 CGPA across academics, Students from Tier I college can apply. Job Description : - You will be responsible for exploring and developing approaches and algorithms for application of data science / machine learning to VLSI design. - Specifically, you will look at how usage of Big data, Machine / deep learning can help attain a better result from placement, clocking, optimization or routing algorithms It will be paid internship, after one year you will be Location : Bangalore Interested students should be available for written test in next week at our campus. Please share your resume @ chetanb@cadence.com

Company : cadence Location : Bangalore Share Your Resume : chetanb@cadence.com

Verification Engineers at Gurgaon India

Job Description: The position requires learning and applying modern verification tools on IC designs. Requirements: Strong educational background with a BTech in Computer Science or Electrical Engineering from an IIT, or an equivalent college. 0-2 years of work experience. Exceptional problem-solving skills. Desirable, but not required: Familiarity with the ASIC design and verification flow.

Company : oskitech Location : Gurgaon Share Your Resume : jobs@oskitech.com

hiring semiconductor freher Marketing Specialist

Designation :- Marketing S_pecialsit Qualification :- B.Sc / B.E ( EEE / ECE) + MBA - Marketing Gender :- Female • Smart, Energetic & Good looking female candidates Work Location :- Chennai • Should be passionate about marketing with positive Work Timing :- 9 am to 6 pm attitude Department :- ASIC / VLSI - Products and Services Only female candidates can apply

Company : mobiveil Location : chennai Share Your Resume : r.nivetha@mobiveil.co.in

Hiring Fresher

i All, I am looking for B.Tech Fresher (2016/17 pass out) with Electronics and Electronics & Telecommunication Branch with 70% Aggregate through education. Available to join us in Bangalore location Please inbox your profile to kirankumar.s@altencalsoftlabs.com

Company : altencalsoftlabs Location : Bangalore Share Your Resume : kirankumar.s@altencalsoftlabs.com

Hiring M Tech Freshers

Hiring M.Tech Freshers from IIT/NIT/VIT/Bits Pilani who passed in year 2016/17 with Primary field as RF/Microwave/Communication/Power Electronics/Antenna for Hyderabad Location. We have multiple openings here. Interested folks can share their resume at aarti.mistry@collabera.com.

Company : collabera Location : Bangalore Share Your Resume : aarti.mistry@collabera.com

DEIGN AND VERIFICATION ENGINEER

we have 20 to 30 position opening on design and verification with minimum experience level of 3 yrs and above

Company : wafer space Location : bangalore,hyderabad,noida,chennai,pune Share Your Resume : hr@supersevak.com, https://www.linkedin.com/feed/update/urn:li:activity:6379229782944595968

physical design engineer

Netlist to GDSII , ICC, INNOVUS spriting language: TCL, PERL, AWK (Additional )

Company : wafer space Location : bangalore Share Your Resume : https://www.linkedin.com/feed/update/urn:li:activity:6379229782944595968

ASIC Design or Verification Engineers

We got a requirement on ASIC Design/Verification Engineer, If you or any of your friends are looking for job Change, share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 2 - 8 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 2 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : ASIC Design or Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: PAN No: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

ASIC Design or Verification Engineers

We got a requirement on ASIC Design/Verification Engineer, If you or any of your friends are looking for job Change, share your update profile to careers@savvychip.com Job Description as follows Requirements: • Experience: 2 - 8 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 2 years of experience can send their Updated profiles to careers@savvychip.com

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

Hiring Verification Engineers at cerium systems

Job description. · BE/B.Tech/ME/M.TECH or equivalent ECE/EEE · 1 to 10 years of experience in SOC Verification · Design and develop test benches using HVLs like System Verilog · Deep expertise in Verification Methodologies like UVM, OVM, VMM · Knowledge of ARM based SoC verification / Interface protocols like PCIe, USB, SATA/SOC verification is essential · Should have experience in creating test plans · Familiarity with scripting languages · Good written and communication skills

Company : cerium systems Location : Bangalore Share Your Resume : dhanasai.pallapolu@cerium-systems.com

VLSI fresher Analog Design layout Standard Cell Memory Layout Engineers

Here is a great opportunity for Analog Design Engineers, Layout Engineers and Standard Cell Engineers and Memory Layout Engineers. Experience Level: 1 to 6 Years. Trained Candidates are also welcome with minimum 6 months but please register your names before 11th March. Analog Design Engineers: Key Skills: Analog Design, Design Engineering, Power Management, pll, phy, digital design, mixed signal, cmos, chip design, cadence, matlab, drc, c, LVS, DFM,ERC. Layout Engineers: Key skills: Piping Layout, Design Engineering, Piping Design, DRC, PDS, PDMS, Detail engineering, Plant Layout, Stress analysis, perl. Standard Cell Engineering: Key Skills: Standard Cell Layout Design, Good understanding in Sub-micron & DFM issues and layout Technology. Memory Layout Engineers: Key Skills: Digital design and timing concepts, ASIC Flow, Full custom flow. IC fabrication techniques, designing using Verilog, Verilog for verification, Exposure to Synthesis, DFT and APR flow.

Company : Pozibility Technologies Location : Bangalore Share Your Resume : kala@pozibility.in

freshers for RTL design Hardware design

LOGIC-FRUIT TECHNOLOGIES is looking for IIT/NIT/IIIT freshers for RTL design & Hardware design positions. Mail me at shangreela.barua@logic-fruit.com.

Company : logic fruit Location : bangalore Share Your Resume : shangreela.barua@logic-fruit.com

ASIC Design and verification Interns at synaptics

Looking for ASIC Design and verification Interns in Bangalore, only M.tech candidates can apply. priyanka.kethidi@in.synaptics.com

Company : synaptics Location : bangalore Share Your Resume : priyanka.kethidi@in.synaptics.com

Hiring VLSI Fresher at ignitarium

Hiring VLSI M Tech Freshen who are interested in Digital Design and Verification FPGA/IP Design ASIC Design Mixed Signal Verification share cv careers@ignitarium.com

Company : ignitarium Location : Bangalore Share Your Resume : careers@ignitarium.com

Zia Semiconductor would be conducting VLSI freshers walkins

Zia Semiconductor would be conducting VLSI freshers walkins Zia Semiconductor would be conducting a walkin for freshers on 06th March 2018. The eligibility criteria would be 85% and above for 10th and 12th and 75% and above in Engineering. Interested candidates can attend the recruitment drive on the above mentioned date at Zia Semiconductor Pvt Ltd, #10, Hosur Road, Langford Town, Shanti Nagar, Near Confident Propus hotel, Bangalore 560025 from 11:00am onwards on 06th March 2018 Bangalore For any queries, please write to: nikhil@ziasemi.com

Company : Zia Semiconductor Location : Bangalore Share Your Resume : nikhil@ziasemi.com

Fresher VLSI Verification Engineers with training experience

Positions: Fresher Verification Engineers with training experience JD & skill requirement: Roles: IP & SOC Verification engineers Qualification:-M tech with training experience Total Experience:- 6months-2+years those who are interested, can forward their resumes to bhagyalakshmi.m@testandverification.com

Company : TEST AND VERIFICATION SOLUTION Location : Bangalore Share Your Resume : bhagyalakshmi.m@testandverification.com

Hiring VLSI freshers at open silicon

Hiring VLSI freshers at open silicon 2018 batch pass outs of MTech specialized in ECE/EEE/VLSI/Electronics

Company : open silicon Location : Bangalore Share Your Resume : careers.india@open-silicon.com

Hiring Trained SoC or CPU Verification VLSI Freshers

Hiring Trained SoC or CPU Verification VLSI Freshers @Bangalore. Good in system verilog uvm and assembly language Mail to: nandap@insilicorp.com

Company : insilicorp Location : Bangalore Share Your Resume : nandap@insilicorp.com

Library Design Engineer

To characterize and release of .libs (liberty files) for 22nm FinFET technologies by using Silicon Smart tool. Simulations are done by FineSim Simulator. In this characterization Power, delay and Noise modelling are done and modelling type is CCS* (CCSN, CCST, CCSP) and NLDM.

Company : intel, bengaluru Location : Bengaluru Share Your Resume : komalkesarwani@outlook.com

Library Design Engineer

To characterize and release of .libs (liberty files) for 22nm FinFET technologies by using Silicon Smart tool. Simulations are done by FineSim Simulator. In this characterization Power, delay and Noise modelling are done and modelling type is CCS* (CCSN, CCST, CCSP) and NLDM.

Company : intel, bengaluru Location : Bengaluru Share Your Resume : komalkesarwani@outlook.com

Physical Design

Experience: 2-6 years "Candidate should be proficient in PnR flow 2. Should be proactive and able to resolve issues independently without much help 3.Decent communication skills to interact with other stake holders Hands-on expertise with technology nodes like 28nm, 16nm and below Expertise with EDA tools from Cadence, Synopsys and Mentor, particularly with Innovus/Encounter, PrimeTime & Calibre

Company : Whizchip Design Technologies Location : Basavanagudi, Gandhi Bazaar Share Your Resume : rakshad@whizchip.com

RTL front end Engineers

Who worked on cdc,lint,LEC,conformal Experience on Synthesis STA

Company : Whizchip design technologies Location : Bangalore Share Your Resume : rekhap@whizchip.com

Verification engineers

Qualification: BE/B.Tech/ME/M.TECH or equivalent ECE/EEE Experience: 3 to 7 years of experience in SOC/IP Verification Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience Must have good communication skills and the ability to work in a team environment. Preferably having experience in architecture such as x86 or ARM domain based SOCs

Company : Whizchip Design Technologies Pvt Ltd Location : Bangalore/Hyderabad Share Your Resume : ankitasen@whizchip.com

frontend Implementation

Who worked o cdc,Lint,LEC,Conformal RTL design with synthesis Exp.

Company : Whizchip design technologies Location : Bangalore Share Your Resume : rekhap@whizchip.com

frontend Implementation

· Hands on experience in Lint (Spyglass), CDC (Spyglass/ZeroIn), LEC (Conformal),STA,DFT · Proficient in scripting languages like Tcl / Perl / Python. · Excellent communication skills and experience in working with multi-site team. RTL/DFT lint, CDC check, Logic equivalence checking

Company : Whizchip design technologies Location : Bangalore Share Your Resume : rekhap@whizchip.com

Memory Design

 Skills and experiences needed:  EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills. ·         Good communication skills. Should be flexible with work and hard working. Should be good in scripting to analysis large data and   summarize. Location Bangalore Use below JD for Memory layout requiremennt 1.       Drawing layouts for schematics created by Design Engineers in 7nm and other FinFET technologies

Company : SiValley Location : Banglore Share Your Resume : www.neugeneinc.com

DFT Trained Freshers

DFT Trained Freshers- We need 10 Engineers who can join Immediately. Share profiles to vlsi_staff@tessolve.com or vlsi.hr@tessolve.com

Company : tessolve Location : Bangalore Share Your Resume : vlsi.hr@tessolve.com

Requirement on Emulation Engineer

Requirements: • Experience: 3 – 6 Years • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. Job Description: • Experience in implementing and debugging designs using FPGAs. • Experience in working on any Emulation platform like ZEBU, Palladium or Veloce. • Experience with HDL simulation, synthesis, and timing closure for FPGA. • Experience on working in SOC. • Experience with Verilog and System Verilog. • Experience in VCS, Synopsys Synplify. • Scripting Knowledge of PERL/PYTHON is added advantage Interested Professionals with minimum of 2 years of experience can send their Updated profiles to careers@savvychip.com Along with below details. All the details would be help full. Note: Including the information as Current Employer Name, Designation, Total Years of Experience, CTC, Exp CTC, Notice Period, Current Location, Contact Number, and Email ID.

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

Junior ASIC Design Verification

Synapse Design, India - hiring Junior Design Verification Engineers(0.6 -1 Year experience) for Bangalore, Candidates with short notice period are encouraged to apply if interested share your CV immediately to lakshminarayana@synapse-da.com

Company : synapse-da Location : Bangalore Share Your Resume : lakshminarayana@synapse-da.com

Physical Design Engineer

#Si2Chip is looking for #PhysicalDesign Professionals #Relevant experience => 3 -10 years. #Location => Bangalore.

Company : Si2chip Location : Bangalore Share Your Resume : himanshu.pandey@si2chip.com

FPGA Engineer

Requirements: • Experience: 3 – 6 Years • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. Job Description: • Experience in implementing and debugging designs using FPGAs. • Experience in working on any Emulation platform like ZEBU, Palladium or Veloce. • Experience with HDL simulation, synthesis, and timing closure for FPGA. • Experience on working in SOC. • Experience with Verilog and System Verilog. • Experience in VCS, Synopsys Synplify. • Scripting Knowledge of PERL or PYTHON is added advantage Interested Professionals with minimum of 2 years of experience can send their Updated profiles to careers@savvychip.com

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

SeviTech is hiring trained fresher for Verification and Synthesis

SeviTech is hiring trained fresher - Someone with 6 months to 9 months experience on the following skills can apply 1. Synthesis 2. Verification Send resumes to aman.ghani@sevitechsystems.com

Company : sevitechsystems Location : Bangalore Share Your Resume : aman.ghani@sevitechsystems.com

digicomm Hiring trained Fresher for PD

Looking for Physical Design trained freshers who can join immediately. Training exp Minimum 6 months Those who are currently in Bangalore are only eligible to apply as we have scheduled Face-to-Face interviews.

Company : digicomm Location : Bangalore Share Your Resume : shalini@digicomm.org

Synopsys hiring Intern positions at Bangalore

Looking for young Engineers for Intern positions at Synopsys,Bengaluru with below detials=> New College graduates, B.E/B.Tech/M.E/M.Tech in Electronics or VLSI background. 1) Should have very good digital logic design knowledge. 2) Knowledge in Verilog/VHDL/FPGA design flow is required. 3) Good communication and inter-personal skills. 4) Exposure to Synplify or any FPGA synthesis software is a plus. Please send your resume to sarasrl@synopsys.com

Company : Synopsys Location : Bangalore Share Your Resume : sarasrl@synopsys.com

Infosys is Hiring Freshers Systems Engineer

Infosys is Hiring Freshers from Batch 2016 and 2017 !!!!!!! Role: Systems Engineer Eligibility Criteria: • BE / B.Tech / ME / M.Tech in any discipline • MCA / MSc (Computer Science / Electronics / Mathematics / Physics / Statistics / IT / Information Science) • Consistently excellent academic track record • Candidates should have graduated during the year 2017 or 2016 • Should not have participated in any selection process with Infosys in the last 9 months Test Location : Bangalore,Kolkata, Pune, Delhi, Chennai , Hyderabad Send me your resume baluabhilash_n@infosys.com. Please message me to Know further Last Date is 23 Feb 2018

Company : Infosys Location : Bangalore Share Your Resume : baluabhilash_n@infosys.com

Intel Hirining IP Design Eng For Bangalore Loaction

ntel Bangalore ASIC RTL DesignSoCIP Design Engineer 2-10 Yrs .Reach me on Srinivasx.k.r@intel.com BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 4+ years of relevant experience in SOC/IP design or MS degree with 2+ years of directly related SOC Design Industry Experience. Candidates must have the following: Expertise in design and integration of design blocks, IPs to system-on-chip components. Experience with designing/dealing with various type of external interfaces, like DDR, PCIe or similar. The ability to work as an individual and as part of a team to deliver a product starting from the creation of the spec, design, verification and support product delivery. Preferred Skills: Experience with ASIC & FPGA based designs. Experience with implementing and working with emulation platforms. Experience in pre and post silicon debug from component and system level

Company : Intel Location : Bangalore Share Your Resume : Srinivasx.k.r@intel.com

VLSI Walk In drive For RTL and FPGA

We have a scheduled drive for 17th Feb (Saturday)at Wafer space office. Domain-RTL/FPGA Design Exp-1yrs Share your updated resume to sasmitap@waferspace.com Shortlisted candidates only can able to attend this drive.

Company : waferspace Location : bangalore Share Your Resume : sasmitap@waferspace.com

DFT Engineer

• Professionals are expected to have good hands-on experience in the following areas: • Complete understanding of DFT concepts and flow (ATPG/Memory BIST//Logic BIST/Scan insertion & Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing) on complex SOCs to improve testability. • Familiarity of any one of the tools (DFT Compiler/RTL Compiler, Testkompress/Tetramax, Virage/Mentor memory BIST, Mentor Bscan) • Test coverage analysis, optimization, Patter Generation/ conversion/ simulation, Time Closure, Area, Power, Performance, Synthesis, STA, Route, Floor Plan, Tester Application Time, Test Data Volume, . • Good scripting skills TCL/Perl/Python

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

Entry level positions open in Analog Layout design From azventa

We have entry-level positions open in Analog Layout design. Fresh graduates with hands-on experience in layout design for LDO, OP-AMP, Current Mirror, ADC, DAC can apply. Qualification: B.Tech. / M.Tech. in Electronics Engineering Minimum CGPA: 8.5 Please send your resume to jobs@azventa.com

Company : azventa Location : bangalore Share Your Resume : jobs@azventa.com

Physical Design Engineer

REQUIREMENTS: • At least 3 to 12 years’ experience in complex ASIC Design projects. • Have in depth knowledge of entire physical design process from floorplan till GDS generation • Have hands-on experience in latest sub-micron technologies below 20nm • Hands –on experience in leading PnR tools Synopsys ICC/Cadence Encounter etc • Experience in low power designs and handling congestion or timing critical tiles will be preferred • Should be a quick learner and have good attention to detail • Experience in ECO implementation preferred • Scripting skills in Perl/Python etc • Must have good communication & problem solving skills. • Should be able to handle PnR tasks with minimal supervision • Bachelor/Master Degree in Electronics Engineering

Company : AMD India Pvt Ltd Location : Hyderabad Share Your Resume : satish-kumar.koneru@amd.com

VLSI fresher Opening at Aricent

We are hiring PD/ PV/ Analog layout trained candidates for our upcoming requirements. We are looking for candidates who have undergone training in VLSI post completion of engineering from any of the training institutes. Please find below the eligibility criteria: B. Tech/B.E/ M. Tech with the percentage of 60 and above. Job Location: Bangalore, Hyderabad, Coimbatore. Training/course completion certificate is mandatory to appear for the interview process. If you have some references please forward us the resumes @raka.mondal@aricent.com You can also direct walk in on 16- Feb-18/ Friday at 11:00AM. Venue: No. 18/1, Outer Ring Road Panathur Post, Opp. to Cisco/ ALOFT Hotel, Bengaluru Karnataka 560103 Contact Person: Raka Mondal

Company : ARICENT Location : Bangalore Share Your Resume : raka.mondal@aricent.com

Hiring VLSI Fresher at synopsys

Hiring for 2017 passout MTech VLSI students with a CGPA of 8 and above. Interested students can share their profile at vishalka@synopsys.com

Company : synopsys Location : Bangalore Share Your Resume : vishalka@synopsys.com

Hirining VLSI Freshers Aricent

hiring Physical design Physical verification Analog layout trained candidates for our upcoming requirements as a trainee. We are looking for candidates who have undergone training in VLSI post completion of engineering from any of the training institutes

Company : www.aricent.com Location : Bangalore Share Your Resume : daljeet.singh@aricent.com

Analog Circuit Designer

• Must have basic Understanding of design circuits like PLL,CDR, DAC, ADC,DC-DC Converter, LDOs, Bandgaps, charge pumps, oscillators, supply monitors, LVDS drivers / receivers, clocking & power management circuits. • Must have experience in using appropriate spice simulators. • Understanding of device physics and demonstrated ability to apply that to optimize noise, power and area. Education : M.Tech - VLSI Job Location : Bangalore

Company : Srotra Technologies Pvt Ltd Location : Bangalore Share Your Resume : vanitha@srotra.com

Sr and Lead Verification Engineer

Job Details : Skill - Functional Verification (IP or SoC) Experience: 2+ years Job location: Hyderabad / Pune / Bangalore/ Noida Skill: System Verilog /OVM/UVM Job Description: Highly motivated engineers responsible for creating testbench and updating existing test benches. Developing test cases and modify the existing test cases with below domain expertize. Ø ARM Based SOC verification (or) DDR Memory Controller verification Ø UVM/OVM based Testbench and sequence development. Ø Expertize on High speed peripheral protocols (PCIe/SATA/USBx) Ø Expertize on Low speed peripheral protocols (I2C/SPI/UART) Ø Expertize on UPF/VCS-NLP, GLS. Ø Functional coverage implementation and coverage analysis.

Company : Smartbytes Technology Location : Bangalore Share Your Resume : girishp@smartbytestech.com

Hiring VLSI fresher at Sichip

Si2Chip is looking for 2018 Passout Students 2017Passout - Please Don't Share your Profile College Tier 1. NOTE:- Please restrain yourself From Sharing Irrelevant Profile.

Company : SiChip Location : Bangalore Share Your Resume : himanshu.pandey@si2chip.com

Memory Layout Engineer

#Si2Chip is looking for #MemoryLayout Professionals #RelevantExperience => 4+ years. #Location => Noida. #KeeySkills => Good Knowledge On FinFet. Relevant folks can share their updated resume @ himanshu.pandey@si2chip.com

Company : Si2chip Location : Bangalore Share Your Resume : himanshu.pandey@si2chip.com

Memory Layout Engineer

#Si2Chip is looking for #MemoryLayout Professionals #RelevantExperience => 4+ years. #Location => Noida. #KeeySkills => Good Knowledge On FinFet. Relevant folks can share their updated resume @ himanshu.pandey@si2chip.com

Company : Si2chip Location : Bangalore Share Your Resume : himanshu.pandey@si2chip.com

VLSI freshers for Design Verification

" Hiring 2016 and 2017 freshers for Design & Verification position. Looking for candidates who have 70% and above percentage and also trained/done internship in System Verilog, UVM. Interviews will be conducted in February-2018. Interested candidates can drop me your resumes to madhav.motakadi@firstpass-semi.com

Company : firstpass-semi Location : Hyderabad Share Your Resume : madhav.motakadi@firstpass-semi.com

Cerium Systems is hiring trained Freshers

Cerium Systems is hiring trained Freshers!!! 1. PD 2. Verification 3. RTL design Send your updated resume to aniket.shelar@cerium-systems.com

Company : cerium-systems Location : Bangalore Share Your Resume : aniket.shelar@cerium-systems.com

VLSI Engineer

Job Role: DXCorr Inviting applications from the fresh Graduates/Postgrauates for VLSI Engineer position. Qualification/Eligibility: BE/B.Tech/M.Tech freshers in Electronics and Communication Engineering/VLSI Design. Experience: Exposure in the VLSI area (Course in VLSI and Internship) would be desirable. Job location: Bangalore,India Please send your resumes to jobs@dxcorr.com with job code 001.

Company : DXCorr Location : Bangalore Share Your Resume : jobs@dxcorr.com

Hiring for ASIC Verification Trainee at SeviTech Systems

SeviTech Systems is Hiring for "Verification Trainee" with M.Tech -VLSI 2017 passed out/ B.Tech 2016 passed out with Internship in verification. Interested candidature can drop resumes to dinesh.c@sevitechsystems.com

Company : sevitechsystems Location : bangalore Share Your Resume : dinesh.c@sevitechsystems.com

RTL Design

Requirements •Experience: 2 - 6 Years in RTL Design. •Education: B.E/B.Tech/M.E/M.tech in ECE/EEE •Work Location : Bangalore Job Description •Strong Experience using Verilog in ASIC flow. •Strong Experience in RTL Integration, Synthesis, STA, ECO, Lint, CDC, and Equilance check techniques. •Should have good knowledge of AXI, AHB, APB, PCIe, USB, Ethernet, SATA, MIPI (CSI, DSI, DPHY, and CPHY) any of these protocols. •Exposure on ARM processor and SoC Integration design will be advantage. Interested Professionals with minimum of 1 years of experience can send their Updated profiles to careers@savvychip.com. Note: Including the information as Current Employer Name, Designation, Total Years of Experience, CTC, Exp CTC, PAN Number, Notice Period, Current Location, Contact Number, and Email ID.

Company : Savvychip Technologies Location : Bangalore Share Your Resume : careers@savvychip.com

Physical Design

2+ Years Experience on top-level floor planning, placement, clock tree synthesis, timing optimization, timing analysis/closure and ECO tasks, (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Should have worked on 45nm or lower node designs Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure detailed knowledge in Cadence or Synopsys physical Design Tools scripting languages such as PERL, TCL

Company : Smartbytes Technology Location : Bangalore Share Your Resume : girishp@smartbytestech.com

STA Engineer

Job Description: • At least 3+ years’ experience in ASIC timing constraints generation and timing closure. • Expertise in STA tools (Primetime) and flow. • Knowledge of timing corners/modes, process variations and signal integrity related issues. • Hands on experience in timing/SDC constraints generation and management. • Proficient in scripting languages (Tcl and Perl). • Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools. • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups. Self-starter and highly motivated. Roles & Responsibilities: • • Create/update timing constraints chip level timing constraints • Should be able to run synthesis analyze timing violations • Debug the issues – identify design and constraint issues • Make edits timing constraints •Create TCL automation scripts for DC/PT tools using attributes Required Skills: • Should be an expert in chip / block level STA • Perl/tcl experience to parse reports/logs and highlight issues STA / Synthesis experience in Synopsys/Cadence tool flows.

Company : Smartbytes Technology Services Location : Bangalore Share Your Resume : kishore.ranjan@smartbytestech.com

Altran is hiring VLSI Freshers

Altran is hiring Freshers(2016/2017 pass out) with M.TECH from VLSI background.if interested please share your updated resume to bindulatha.donthi@altran.com

Company : altran Location : Bangalore Share Your Resume : bindulatha.donthi@altran.com