Verilog Operators

✼ Operators in Verilog are symbols used to perform operations on values or variables, similar to those in C programming.

✼ Verilog operators serve various purposes and are categorized into different types. Commonly used categories of Verilog operators include:

Arithmetic Operators

Arithmetic Operators Used for arithmetic calculations such as addition, subtraction, multiplication, division, and modulus.

Operator	Description	Example
+	Performs addition of two operands	result = operand1 + operand2;
-	Performs subtraction of the second operand from the first operand	result = operand1 - operand2;
*	Performs multiplication of two operands	result = operand1 * operand2;
/	Performs division of the first operand by the second operand	result = operand1 / operand2;
%	Calculates the remainder when the first operand is divided by the second operand	result = operand1 % operand2;

Operator

Description

Example

Performs addition of two operands

result = operand1 + operand2;

Performs subtraction of the second operand from the first operand

result = operand1 - operand2;

Performs multiplication of two operands

result = operand1 * operand2;

Performs division of the first operand by the second operand

result = operand1 / operand2;

Calculates the remainder when the first operand is divided by the second operand

result = operand1 % operand2;

Example

Addition

module add_example;
  reg [3:0] a, b;
  wire [4:0] sum;

  assign sum = a + b;

  initial begin
    a = 4'b0101;
    b = 4'b0011;
    #1 $display("Sum of %b and %b is %b", a, b, sum);
  end
endmodule



Subtraction

module sub_example;
  reg [7:0] a, b;
  wire [7:0] diff;

  assign diff = a - b;

  initial begin
    a = 8'd100;
    b = 8'd25;
    #1 $display("Difference of %d and %d is %d", a, b, diff);
  end
endmodule

Multiplication

module mult_example;
  reg [7:0] a, b;
  wire [15:0] product;

  assign product = a * b;

  initial begin
    a = 8'd10;
    b = 8'd12;
    #1 $display("Product of %d and %d is %d", a, b, product);
  end
endmodule

Division

module div_example;
  reg [15:0] a;
  reg [7:0] b;
  wire [7:0] quotient;
  wire [7:0] remainder;

  assign {remainder, quotient} = a / b;

  initial begin
    a = 16'd100;
    b = 8'd4;
    #1 $display("Quotient of %d / %d is %d, Remainder is %d", a, b, quotient, remainder);
  end
endmodule

Modulus

module mod_example;
  reg [7:0] a, b;
  wire [7:0] mod_result;

  assign mod_result = a % b;

  initial begin
    a = 8'd17;
    b = 8'd5;
    #1 $display("Modulus of %d %% %d is %d", a, b, mod_result);
  end
endmodule

module power_example;
  reg [3:0] a, b;
  wire [7:0] power_result;

  assign power_result = a ** b;

  initial begin
    a = 3;
    b = 4;
    #1 $display("Power of %d raised to %d is %d", a, b, power_result);
  end
endmodule


module arithmetic_ops;
    reg [7:0] a, b;
    wire [7:0] sum, diff, prod, quot, rem;
    assign sum = a + b;
    assign diff = a - b;
    assign prod = a * b;
    assign quot = a / b;
    assign rem = a % b;

    initial begin
        a = 8'd10;
        b = 8'd3;
        $display("a = %d, b = %d", a, b);
        $display("sum = %d, diff = %d, prod = %d, quot = %d, rem = %d", sum, diff, prod, quot, rem);
    end
endmodule

Logical Operators in Verilog

Logical Operators Used for logical operations such as AND, OR, and NOT.

Operator	Description	Example
&&	Logical AND operator	result = operand1 && operand2;
\|\|	Logical OR operator	result = operand1 \|\| operand2;
!	Logical NOT operator	result = !operand1;
&	Bitwise AND operator	result = operand1 & operand2;
\|	Bitwise OR operator	result = operand1 \| operand2;

Operator

Description

Example

Logical AND operator

result = operand1 && operand2;

Logical OR operator

result = operand1 || operand2;

Logical NOT operator

result = !operand1;

Bitwise AND operator

result = operand1 & operand2;

Bitwise OR operator

result = operand1 | operand2;

Example

module logical_operators;

  // Example 1: Logical AND
  reg [3:0] a1, b1;
  wire [3:0] and_result;
  assign and_result = a1 & b1;

  // Example 2: Logical OR
  reg [3:0] a2, b2;
  wire [3:0] or_result;
  assign or_result = a2 | b2;

  // Example 3: Logical XOR
  reg [3:0] a3, b3;
  wire [3:0] xor_result;
  assign xor_result = a3 ^ b3;

  // Example 4: Logical NAND
  reg [3:0] a4, b4;
  wire [3:0] nand_result;
  assign nand_result = ~(a4 & b4);

  // Example 5: Logical NOR
  reg [3:0] a5, b5;
  wire [3:0] nor_result;
  assign nor_result = ~(a5 | b5);

  // Example 6: Logical XNOR
  reg [3:0] a6, b6;
  wire [3:0] xnor_result;
  assign xnor_result = ~(a6 ^ b6);

  // Example 7: Logical Negation
  reg [3:0] a7;
  wire [3:0] neg_result;
  assign neg_result = ~a7;

  initial begin
    // Example 1
    a1 = 4'b1010;
    b1 = 4'b0101;
    #1 $display("AND of %b and %b is %b", a1, b1, and_result);

    // Example 2
    a2 = 4'b1010;
    b2 = 4'b0101;
    #1 $display("OR of %b and %b is %b", a2, b2, or_result);

    // Example 3
    a3 = 4'b1010;
    b3 = 4'b0101;
    #1 $display("XOR of %b and %b is %b", a3, b3, xor_result);

    // Example 4
    a4 = 4'b1010;
    b4 = 4'b0101;
    #1 $display("NAND of %b and %b is %b", a4, b4, nand_result);

    // Example 5
    a5 = 4'b1010;
    b5 = 4'b0101;
    #1 $display("NOR of %b and %b is %b", a5, b5, nor_result);

    // Example 6
    a6 = 4'b1010;
    b6 = 4'b0101;
    #1 $display("XNOR of %b and %b is %b", a6, b6, xnor_result);

    // Example 7
    a7 = 4'b1010;
    #1 $display("Negation of %b is %b", a7, neg_result);
  end

endmodule

Bitwise Operators in Verilog

Bitwise Operators Used for bit-level manipulation and operations, including AND, OR, XOR, complement, left shift, and right shift.

Operator	Description	Example
&	Bitwise AND operator	result = operand1 & operand2;
\|	Bitwise OR operator	result = operand1 \| operand2;
^	Bitwise XOR (exclusive OR) operator	result = operand1 ^ operand2;
~	Bitwise NOT (complement) operator	result = ~operand1;
<<	Left shift operator	result = operand1 << n;
>>	Right shift operator	result = operand1 >> n;

Operator

Description

Example

Bitwise AND operator

result = operand1 & operand2;

Bitwise OR operator

result = operand1 | operand2;

Bitwise XOR (exclusive OR) operator

result = operand1 ^ operand2;

Bitwise NOT (complement) operator

result = ~operand1;

Left shift operator

result = operand1 << n;

Right shift operator

result = operand1 >> n;

Example

module bitwise_operators;

  // Example 1: Bitwise AND
  reg [7:0] a1, b1;
  wire [7:0] and_result;
  assign and_result = a1 & b1;

  // Example 2: Bitwise OR
  reg [7:0] a2, b2;
  wire [7:0] or_result;
  assign or_result = a2 | b2;

  // Example 3: Bitwise XOR
  reg [7:0] a3, b3;
  wire [7:0] xor_result;
  assign xor_result = a3 ^ b3;

  // Example 4: Bitwise NAND
  reg [7:0] a4, b4;
  wire [7:0] nand_result;
  assign nand_result = ~(a4 & b4);

  // Example 5: Bitwise NOR
  reg [7:0] a5, b5;
  wire [7:0] nor_result;
  assign nor_result = ~(a5 | b5);

  // Example 6: Bitwise XNOR
  reg [7:0] a6, b6;
  wire [7:0] xnor_result;
  assign xnor_result = ~(a6 ^ b6);

  // Example 7: Bitwise Negation
  reg [7:0] a7;
  wire [7:0] neg_result;
  assign neg_result = ~a7;

  // Example 8: Bitwise Left Shift
  reg [7:0] a8;
  reg [2:0] shift_amount8;
  wire [7:0] shl_result;
  assign shl_result = a8 << shift_amount8;

  // Example 9: Bitwise Right Shift
  reg [7:0] a9;
  reg [2:0] shift_amount9;
  wire [7:0] shr_result;
  assign shr_result = a9 >> shift_amount9;

  // Example 10: Bitwise Arithmetic Right Shift
  reg signed [7:0] a10;
  reg [2:0] shift_amount10;
  wire signed [7:0] ashr_result;
  assign ashr_result = a10 >>> shift_amount10;

  initial begin
    // Example 1
    a1 = 8'b10101010;
    b1 = 8'b01010101;
    #1 $display("Bitwise AND of %b and %b is %b", a1, b1, and_result);

    // Example 2
    a2 = 8'b10101010;
    b2 = 8'b01010101;
    #1 $display("Bitwise OR of %b and %b is %b", a2, b2, or_result);

    // Example 3
    a3 = 8'b10101010;
    b3 = 8'b01010101;
    #1 $display("Bitwise XOR of %b and %b is %b", a3, b3, xor_result);

    // Example 4
    a4 = 8'b10101010;
    b4 = 8'b01010101;
    #1 $display("Bitwise NAND of %b and %b is %b", a4, b4, nand_result);

    // Example 5
    a5 = 8'b10101010;
    b5 = 8'b01010101;
    #1 $display("Bitwise NOR of %b and %b is %b", a5, b5, nor_result);

    // Example 6
    a6 = 8'b10101010;
    b6 = 8'b01010101;
    #1 $display("Bitwise XNOR of %b and %b is %b", a6, b6, xnor_result);

    // Example 7
    a7 = 8'b10101010;
    #1 $display("Bitwise Negation of %b is %b", a7, neg_result);

    // Example 8
    a8 = 8'b10101010;
    shift_amount8 = 3'd2;
    #1 $display("Bitwise Left Shift of %b by %d is %b", a8, shift_amount8, shl_result);

    // Example 9
    a9 = 8'b10101010;
    shift_amount9 = 3'd2;
    #1 $display("Bitwise Right Shift of %b by %d is %b", a9, shift_amount9, shr_result);

    // Example 10
    a10 = 8'd100;
    shift_amount10 = 3'd2;
    #1 $display("Bitwise Arithmetic Right Shift of %d by %d is %d", a10, shift_amount10, ashr_result);
  end

endmodule

Relational Operators in Verilog

Relational Operators Used for comparing values and determining relationships, such as equal to, not equal to, greater than, and less than.

Operator	Description	Example
==	Equal to operator	result = operand1 == operand2;
!=	Not equal to operator	result = operand1 != operand2;
>	Greater than operator	result = operand1 > operand2;
>=	Greater than or equal to operator	result = operand1 >= operand2;
<	Less than operator	result = operand1 < operand2;
⇐	Less than or equal to operator	result = operand1 ⇐ operand2;

Operator

Description

Example

Equal to operator

result = operand1 == operand2;

Not equal to operator

result = operand1 != operand2;

Greater than operator

result = operand1 > operand2;

Greater than or equal to operator

result = operand1 >= operand2;

Less than operator

result = operand1 < operand2;

⇐

Less than or equal to operator

result = operand1 ⇐ operand2;

Example

module relational_ops;

reg [7:0] a, b;
wire equal, not_equal, less_than, less_than_equal, greater_than, greater_than_equal;

assign equal = (a == b);
assign not_equal = (a != b);
assign less_than = (a < b);
assign less_than_equal = (a <= b);
assign greater_than = (a > b);
assign greater_than_equal = (a >= b);

initial begin
    a = 8'd10;
    b = 8'd3;

    $display("a = %d, b = %d", a, b);
    $display("equal = %b, not_equal = %b", equal, not_equal);
    $display("less_than = %b, less_than_equal = %b", less_than, less_than_equal);
    $display("greater_than = %b, greater_than_equal = %b", greater_than, greater_than_equal);
end

endmodule

Assignment Operators in Verilog

Assignment Operators Used for assigning values to variables, including simple assignment and compound assignment operators like add and assign, subtract and assign, multiply and assign, etc.

Operator	Description	Example
=	Simple assignment operator	operand1 = operand2;
+=	Add and assignment operator	operand1 += operand2;
-=	Subtract and assignment operator	operand1 -= operand2;
*=	Multiply and assignment operator	operand1 *= operand2;
/=	Divide and assignment operator	operand1 /= operand2;
%=	Modulo and assignment operator	operand1 %= operand2;
&=	Bitwise AND and assignment operator	operand1 &= operand2;
	=	Bitwise OR and assignment operator
operand1	= operand2;	^=
Bitwise XOR and assignment operator	operand1 ^= operand2;	<⇐
Left shift and assignment operator	operand1 <⇐ n;	>>=

Operator

Description

Example

Simple assignment operator

operand1 = operand2;

Add and assignment operator

operand1 += operand2;

Subtract and assignment operator

operand1 -= operand2;

Multiply and assignment operator

operand1 *= operand2;

Divide and assignment operator

operand1 /= operand2;

Modulo and assignment operator

operand1 %= operand2;

Bitwise AND and assignment operator

operand1 &= operand2;

Bitwise OR and assignment operator

operand1

= operand2;

Bitwise XOR and assignment operator

operand1 ^= operand2;

<⇐

Left shift and assignment operator

operand1 <⇐ n;

>>=

Example

module assignment_ops;

reg [7:0] a, b, c;

initial begin
    a = 8'd10;
    b = 8'd3;
    c = 8'd0;

    $display("Initial values: a = %d, b = %d, c = %d", a, b, c);

    // Simple assignment
    c = a;
    $display("After simple assignment: a = %d, b = %d, c = %d", a, b, c);

    // Compound addition assignment
    c += b;
    $display("After compound addition: a = %d, b = %d, c = %d", a, b, c);

    // Compound subtraction assignment
    c -= a;
    $display("After compound subtraction: a = %d, b = %d, c = %d", a, b, c);

    // Compound multiplication assignment
    c *= b;
    $display("After compound multiplication: a = %d, b = %d, c = %d", a, b, c);

    // Compound division assignment
    c /= a;
    $display("After compound division: a = %d, b = %d, c = %d", a, b, c);

    // Compound modulus assignment
    c %= b;
    $display("After compound modulus: a = %d, b = %d, c = %d", a, b, c);

    // Compound bitwise AND assignment
    c &= a;
    $display("After compound bitwise AND: a = %d, b = %d, c = %d", a, b, c);

    // Compound bitwise OR assignment
    c |= b;
    $display("After compound bitwise OR: a = %d, b = %d, c = %d", a, b, c);

    // Compound bitwise XOR assignment
    c ^= a;
    $display("After compound bitwise XOR: a = %d, b = %d, c = %d", a, b, c);
end

endmodule

Concatenation and Replication Operators

Concatenation Operator Used to combine multiple values or variables into a single value. It is represented by the {} symbols.

Replication Operator Used to replicate a value or a pattern multiple times. It is represented by the {n{value}} syntax, where n is the number of times to replicate the value.

Operator	Description	Example
{ }	Concatenation operator	result = {operand1, operand2};
{n{}}	Replication operator	result = {4{operand}};

Operator

Description

Example

{ }

Concatenation operator

result = {operand1, operand2};

{n{}}

Replication operator

result = {4{operand}};

Example

module concat_replication_ops;

reg [3:0] a, b;
wire [7:0] concat_result;
wire [11:0] replication_result;

// Concatenation
assign concat_result = {a, b};

// Replication
assign replication_result = {3{a, b}};

initial begin
    a = 4'b1010;
    b = 4'b0101;

    $display("a = %b, b = %b", a, b);
    $display("Concatenation result: %b", concat_result);
    $display("Replication result: %b", replication_result);
end

endmodule