vlsijobseeker
.COM
Home
About
Contact
VLSI Jobs
VerilogHDL
VerilogHDL
1. Introduction to Verilog HDL
2. Verilog Primitives and Data Types
3. Verilog Operators and Expressions
4. Verilog Gate-Level Modeling
5. Verilog Behavioral Modeling
6. Verilog Tasks and Functions
7. Verilog Testbench and Verification
8. Verilog Synthesis Constructs
9. Verilog Timing and Delay Models
10. Verilog for Programmable Logic Devices
SystemVerilog
SystemVerilog HDVL
1. Introduction to SystemVerilog
2. SystemVerilog Data Types and Operators
3. SystemVerilog Interfaces and Packages
4. SystemVerilog Assertions and Functional Coverage
5. SystemVerilog Constrained Random Verification
6. SystemVerilog Object-Oriented Programming
7. SystemVerilog Testbench and Verification Components
8. SystemVerilog Synthesis and Low-Power Design
9. SystemVerilog for Accelerated Verification
10. SystemVerilog for Emulation and FPGA-Based Prototyping
UVM (Universal Verification Methodology)
UVM
1. Introduction to UVM
2. UVM Testbench Architecture
3. UVM Sequences and Sequencers
4. UVM Scoreboards and Data Checkers
5. UVM Callbacks and Transactions
6. UVM Constrained Random Verification
7. UVM Functional Coverage and Assertions
8. UVM Reporting and Debug Utilities
9. UVM Reusability and Portability
10. UVM for Advanced Verification Techniques
SystemVerilog Assertions (SVA)
SystemVerilog Assertions (SVA)
1. Introduction to SystemVerilog Assertions
2. Immediate Assertions
3. Concurrent Assertions
4. Clocking and Sampling
5. Advanced SVA Concepts
6. SVA for Formal Verification
7. SVA for Functional Coverage
8. SVA Coding Guidelines
9. SVA and UVM Integration
10. SVA Case Studies and Examples
Digital Electronics
Digital Electronics
1. Introduction to Digital Electronics
2. Number Systems and Codes Standards
3. Logic Gate and Boolean Algebra Standards
4. Combinational Logic Circuit Standards
5. Sequential Logic Circuit Standards
6. Counter and Shift Register Standards
7. Memory Device Standards
8. Analog-to-Digital and Digital-to-Analog Converter Standards
9. Programmable Logic Device Standards
10.EEE Digital System Design and Verification Standards
Other Courses
VLSI DESIGN FLOW
Memory Design & Verification
Test Plan for FIFO design & Verification
RISC-V
Chapter 4
Chapter 5
Content Information
When you click on a link from the course content, the corresponding information will be displayed here in a new tab.
Contact Us
Scan the QR code or click the WhatsApp icon to get in touch with us.
FOR VLSI JOBS NOTIFICATION FOLLOW US
VLSI Job Listings
×
Job Title 1
Job description goes here...
Job Title 2
Job description goes here...
Job Title 3
Job description goes here...